System and method for energy-efficient implementation of neural networks
A system and method for enhancing C*RAM, improving its performance for known applications such as video processing but also making it well suited to low-power implementation of neural nets. The required computing engine is decomposed into banks of enhanced C*RAM each having a SIMD controller, thus allowing operations at several scales simultaneously. Several configurations of suitable controllers are discussed, along with communication structures and enhanced processing elements.
1. A device comprising:
memory;
a plurality of processing elements for performing parallel operations using the memory;
a plurality of controllers for controlling the plurality of processing elements wherein one or more of the plurality of controllers are configured to control a plurality of segment switches;
a column bus operable to unidirectionally or bidirectionally communicate information among any of the plurality of processing elements, wherein the column bus is segmented and wherein the plurality of controllers are interconnected by the column bus and are configured to share information via the column bus; and
a row bus segmented by the plurality of segment switches, the row bus operable to unidirectionally or bidirectionally communicate information among any of the plurality of controllers and the plurality of processing elements, wherein the row bus is segmented to provide pipelined flow of information among segments of the row bus.
2. The device of claim 1 , wherein a direction of the row bus is set by the plurality of controllers.
3. The device of claim 1 , wherein a direction of the row bus is set by a state of one or more of the plurality of processing elements.
4. The device of claim 1 , wherein the row bus is configured to provide opcodes.
5. The device of claim 1 , wherein at least one of the processing elements comprises a multiplexer configured to put information onto the row bus.
6. The device of claim 5 , wherein the multiplexer is further configured to take information from the row bus.
7. The device of claim 1 , wherein the row bus is wire-ANDed.
8. The device of claim 1 , wherein the row bus is segmented by latching.
9. The device of claim 1 , wherein one or more of the plurality of processing elements is configured to control the plurality of segment switches.
10. The device of claim 1 , further comprising a plurality of row buses, each row bus of the plurality of row buses operable to unidirectionally or bidirectionally communicate information among any of the plurality of controllers and the plurality of processing elements, wherein at least two of the plurality of row buses are segmented to a different degree.
11. A device comprising:
a plurality of banks, each bank including memory and a plurality of processing elements for performing parallel operations using the memory;
a plurality of controllers for controlling the plurality of processing elements wherein the plurality of controllers are configured to control a plurality of segment switches;
a column bus operable to unidirectionally or bidirectionally communicate information among any of the plurality of processing elements, wherein the column bus is segmented by the plurality of segment switches and wherein the plurality of controllers are interconnected by the column bus and are configured to share information via the column bus; and
a row bus operable to unidirectionally or bidirectionally communicate information among any of the plurality of controllers and the plurality of processing elements, wherein the row bus is segmented.
12. The device of claim 11 , wherein the column bus is operable to unidirectionally or bidirectionally communicate information among any of the plurality of controllers and the plurality of processing elements.
13. The device of claim 11 , wherein a direction of column bus is set by the plurality of controllers.
14. The device of claim 11 , wherein a direction of the column bus is set by a state of one or more of the plurality of processing elements.
15. The device of claim 11 , wherein the column bus is configured to provide opcodes.
16. The device of claim 11 , wherein at least one of the processing elements comprises a multiplexer configured to put information onto the column bus.
17. The device of claim 16 , wherein the multiplexer is further configured to take information from the column bus.
18. The device of claim 11 , wherein the column bus is wire-ANDed.
19. The device of claim 11 , wherein the column bus is segmented by latching.
20. The device of claim 11 , wherein one or more of the plurality of processing elements is configured to control the plurality of segment switches.
21. The device of claim 11 , further comprising a plurality of column buses, each column bus of the plurality of column buses operable to unidirectionally or bidirectionally communicate information among any of the plurality of controllers and the plurality of processing elements, wherein at least two of the column buses are segmented to a different degree.
22. The device of claim 11 , wherein the plurality of controllers have nearest-neighbor interconnections configured to enable synchronization.
23. The device of claim 11 , wherein the plurality of controllers are interconnected by the column bus are configured to share decoded instructions via the column bus.
24. The device of claim 11 , wherein the row bus is segmented by latching.
25. The device of claim 11 , wherein the row bus is segmented by the plurality of segment switches.
26. A device comprising:
memory;
a plurality of processing elements for performing parallel operations using the memory, wherein one or more of the plurality of processing elements is configured to control a plurality of segment switches;
a plurality of controllers for controlling the plurality of processing elements;
a column bus operable to unidirectionally or bidirectionally communicate information among any of the plurality of processing elements, wherein the column bus is segmented and wherein the plurality of controllers are interconnected by the column bus and are configured to share information via the column bus; and
a row bus segmented by the plurality of segment switches, the row bus operable to unidirectionally or bidirectionally communicate information among any of the plurality of controllers and the plurality of processing elements, wherein the row bus is segmented to provide pipelined flow of information among segments of the row bus.
27. A device comprising:
memory;
a plurality of processing elements for performing parallel operations using the memory;
a plurality of controllers for controlling the plurality of processing elements;
a column bus operable to unidirectionally or bidirectionally communicate information among any of the plurality of processing elements, wherein the column bus is segmented and wherein the plurality of controllers are interconnected by the column bus and are configured to share information via the column bus; and
a plurality of row buses, each row bus operable to unidirectionally or bidirectionally communicate information among any of the plurality of controllers and the plurality of processing elements, wherein at least two row buses of the plurality of row buses are segmented to provide pipelined flow of information among segments of the plurality of row buses, and wherein the at least two row buses of the plurality of row buses are segmented to a different degree.
28. A device comprising:
a plurality of banks, each bank including memory and a plurality of processing elements for performing parallel operations using the memory;
a plurality of controllers for controlling the plurality of processing elements;
a plurality of column buses, each column bus of the plurality of column buses operable to unidirectionally or bidirectionally communicate information among any of the plurality of controllers and the plurality of processing elements, wherein the plurality of controllers are interconnected by the plurality of column buses and are configured to share information via the plurality of column buses, wherein the plurality of column buses are segmented and at least two column buses of the plurality of column buses are segmented to a different degree; and
a row bus operable to unidirectionally or bidirectionally communicate information among any of the plurality of controllers and the plurality of processing elements, wherein the row bus is segmented.