System and method to control memory failure handling on double-data rate dual in-line memory modules via suspension of the collection of correctable read errors
An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. The failure predictor receives a first in time interrupt, suspends the accumulation of the count for a first duration of time in response to receiving the first in time interrupt, and resumes the accumulation of the count. In resuming the accumulation of the count, the failure predictor increments the count each time the predictor receives a first subsequent interrupt and decrements the count in accordance with an error leak rate.
1. An information handling system, comprising:
a processor;
a dual in-line memory module (DIMM); and
a memory controller coupled to the DIMM, the memory controller configured to determine that a read transaction from the DIMM results in a correctable read error, and to provide interrupts to the processor each time the read transaction from the DIMM results in the correctable read error;
wherein the processor is configured to instantiate a failure predictor to receive the interrupts, to accumulate a count of the interrupts, and to provide a first error indication when the count exceeds a first error threshold, wherein in accumulating the count, the failure predictor receives a first in time interrupt, suspends the accumulation of the count for a first duration of time in response to receiving the first in time interrupt, and resumes the accumulation of the count after the first duration of time, wherein in resuming the accumulation of the count the failure predictor receives a first subsequent interrupt, increments the count each time the predictor receives the first subsequent interrupt and decrements the count in accordance with an error leak rate.
2. The information handling system of claim 1 , wherein the first duration of time is based upon a first transient condition on the information handling system.
3. The information handling system of claim 2 , further comprising:
a service processor configured to detect the first transient condition on the information handling system, wherein the failure predictor further receives first status information from the service processor based on the first transient condition and determines the first time duration based on the first status information.
4. The information handling system of claim 3 , wherein the service processor is further configured to detect a second transient condition on the information handling system.
5. The information handling system of claim 4 , wherein the failure predictor further receives second status information from the service processor based on the second transient condition, and determines a second time duration based on the second status information.
6. The information handling system of claim 5 , wherein in accumulating the count, the failure predictor further receives a second in time interrupt, suspends the accumulation of the count for the second duration of time in response to receiving the second in time interrupt, and resumes the accumulation of the count after the second duration of time, wherein in resuming the accumulation of the count the failure predictor receives a second subsequent interrupt, increments the count each time the predictor receives the second subsequent interrupt, and decrements the count in accordance with an error leak rate.
7. The information handling system of claim 2 , wherein the first transient condition on the information handling system comprises one of noise on a voltage regulator of the information handling system, crosstalk from a first circuit of the information handling system, and detected errors on a second circuit of the information handling system.
8. The information handling system of claim 1 , wherein the failure predictor is included in an interrupt handler of the information handling system.
9. A method of controlling a dual in-line memory module (DIMM), comprising:
determining, by a memory controller of the information handling system, that a read transaction from the DIMM results in a correctable read error;
providing, by the memory controller, interrupts to a processor of the information handling system each time a read transaction between the memory controller and the DIMM results in the correctable read error;
receiving, by a failure predictor instantiated by the processor, the interrupts;
accumulating, by the failure predictor, a count of the interrupts; and
providing, by the failure predictor, a first error indication when the count exceeds a first error threshold;
wherein in accumulating the count the method further comprises:
receiving a first in time interrupt;
suspending the accumulation of the count for a first duration of time in response to receiving the first in time interrupt; and
resuming the accumulation of the count after the first duration of time;
wherein in resuming the accumulation of the count the method further comprises:
receiving a first subsequent interrupt;
incrementing the count each time the predictor receives the first subsequent interrupt; and
decrementing the count in accordance with an error leak rate.
10. The method of claim 9 , wherein the first duration of time is based upon a first transient condition on the information handling system.
11. The method of claim 10 , further comprising:
detecting, by a service processor of the information handling system, the first transient condition on the information handling system;
receiving, by the failure predictor, first status information from the service processor based on the first transient condition; and
determining, by the failure predictor, the first time duration based on the first status information.
12. The method of claim 11 , further comprising:
detecting, by the service processor, a second transient condition on the information handling system.
13. The method of claim 12 , further comprising:
receiving, by the failure predictor, second status information from the service processor based on the second transient condition; and
determining, by the failure predictor, a second time duration based on the second status information.
14. The method of claim 13 , wherein:
in accumulating the count the method further comprises:
receiving a second in time interrupt;
suspending the accumulation of the count for the second duration of time in response to receiving the second in time interrupt; and
resuming the accumulation of the count after the second duration of time;
wherein in resuming the accumulation of the count the method further comprises:
receiving a second subsequent interrupt;
incrementing the count each time the predictor receives the second subsequent interrupt; and
decrementing the count in accordance with an error leak rate.
15. The method of claim 10 , wherein the first transient condition on the information handling system comprises one of noise on a voltage regulator of the information handling system, crosstalk from a first circuit of the information handling system, and detected errors on a second circuit of the information handling system.
16. The method of claim 9 , wherein the failure predictor is included in an interrupt handler of the information handling system.
17. An information handling system, comprising:
a processor;
a dual in-line memory module (DIMM); and
a memory controller coupled to the DIMM, the memory controller configured to
determine that a read transaction from the DIMM results in a correctable read error, and to provide interrupts to the processor each time the read transaction from the DIMM results in a correctable read error;
wherein the processor includes an interrupt handler configured to instantiate a failure predictor, the failure predictor to receive the interrupts, to accumulate a count of the interrupts, and to provide a first error indication when the count exceeds a first error threshold, wherein in accumulating the count, the failure predictor receives a first in time interrupt, suspends the accumulation of the count for a first duration of time in response to receiving the first in time interrupt, and resumes the accumulation of the count after the first duration of time, wherein in resuming the accumulation of the count the failure predictor receives a second subsequent interrupt, increments the count each time the predictor receives the first subsequent interrupt, and decrements the count in accordance with an error leak rate, and wherein the first duration of time is based upon a first transient condition on the information handling system.
18. The information handling system of claim 17 , further comprising:
a service processor configured to detect the first transient condition on the information handling system, wherein the failure predictor further receives first status information from the service processor based on the first transient condition and determines the first time duration based on the first status information.
19. The information handling system of claim 18 , wherein the first transient condition on the information handling system comprises one of noise on a voltage regulator of the information handling system, crosstalk from a first circuit of the information handling system, and detected errors on a second circuit of the information handling system.
20. The information handling system of claim 17 , wherein the failure predictor is included in an interrupt handler of the information handling system.