IP Library Granted Patent US 10,103,910
Granted Patent B1
US 10,103,910 · App. 15/903,978 · Granted Oct 16, 2018

Pulse amplitude modulation equalization optimization system

Inventors: Umesh Chandra (Santa Cruz, CA); Bhyrav M. Mutnury (Austin, TX); Arun Reddy Chada (Round Rock, TX); Han Deng (Round Rock, TX)
Assignee: Dell Products L.P.
H04L25/03949H04L1/0072H04L25/03038
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,103,910
App. No.
15/903,978
Granted
Oct 16, 2018
Kind
B1
Abstract

A PAM equalization optimization system includes a BIOS coupled to a PAM engine and an equalization engine. The BIOS determines an effective equalization tap number of equalization taps that each provide an equalization result above a predetermined amount. The BIOS then determines whether the effective equalization tap number is greater than a predetermined fraction of an available equalization tap number of equalization taps that are available for equalizing a signal. When the effective equalization tap number is greater than the predetermined fraction of the available equalization tap number, the BIOS causes the equalization engine to perform per-symbol equalization on signals modulated using the PAM engine. When the effective equalization tap number is not greater than the predetermined fraction of the available equalization tap number, the BIOS causes the equalization engine to perform per-bit equalization on signals modulated using the PAM engine.

Claims (48)

1. A pulse amplitude modulation equalization optimization system, comprising:

a Pulse Amplitude Modulation (PAM) engine;

an equalization engine that is coupled to the PAM engine; and

a Basic Input/Output System (BIOS) that is coupled to the PAM engine and the equalization engine, wherein the BIOS is configured to:

determine an effective equalization tap number that is indicative of a number of equalization taps that each provide an equalization result above a predetermined amount;

determine whether the effective equalization tap number is greater than a predetermined fraction of an available equalization tap number, wherein the available equalization tap number is indicative of a number of equalization taps that are available for equalizing a signal;

cause, when the effective equalization tap number is greater than the predetermined fraction of the available equalization tap number, the equalization engine to perform per-symbol equalization on signals modulated using the PAM engine; and

cause, when the effective equalization tap number is not greater than the predetermined fraction of the available equalization tap number, the equalization engine to perform per-bit equalization on signals modulated using the PAM engine.

2. The system of claim 1 , wherein the PAM engine is configured to modulate signals using a four level PAM scheme (PAM4).

3. The system of claim 1 , wherein the equalization engine is configured to perform Feed Forward Equalization (FFE).

4. The system of claim 1 , wherein the equalization result that is above the predetermined amount includes an equalized signal change that is greater or equal to one percent.

5. The system of claim 1 , wherein the predetermined fraction of the available equalization tap number is half the available equalization tap number.

6. The system of claim 1 , wherein the BIOS is configured to:

perform link training operations in a pre-boot environment; and

complete the link training operations prior to determining the effective equalization tap number in the pre-boot environment.

7. The system of claim 1 , wherein the BIOS is configured to:

perform link training operations in a runtime environment; and

complete the link training operations prior to determining the effective equalization tap number in the runtime environment.

8. An Information Handling System (IHS), comprising:

a modulation subsystem;

a processing system that is coupled to the modulation subsystem; and

a memory system that is coupled to the processing system and that includes instruction that, when executed by the processing system, cause the processing system to perform operations comprising:

determining an effective equalization tap number that is indicative of a number of equalization taps that each provide an equalization result above a predetermined amount;

determining whether the effective equalization tap number is greater than a predetermined fraction of an available equalization tap number, wherein the available equalization tap number is indicative of a number of equalization taps that are available for equalizing a signal;

causing, when the effective equalization tap number is greater than the predetermined fraction of the available equalization tap number, the modulation subsystem to perform per-symbol equalization on signals modulated using Pulse Amplitude Modulation (PAM); and

causing, when the effective equalization tap number is not greater than the predetermined fraction of the available equalization tap number, the modulation subsystem to perform per-bit equalization on signals modulated using PAM.

9. The IHS of claim 8 , wherein the signals are modulated using four level PAM (PAM4).

10. The IHS of claim 8 , wherein the equalization is Feed Forward Equalization (FFE).

11. The IHS of claim 8 , wherein the equalization result that is above the predetermined amount includes an equalized signal change that is greater or equal to one percent.

12. The IHS of claim 8 , wherein the predetermined fraction of the available equalization tap number is half the available equalization tap number.

13. The IHS of claim 8 , wherein the BIOS is configured to:

perform link training operations in a pre-boot environment; and

complete the link training operations prior to determining the effective equalization tap number in the pre-boot environment.

14. A pulse amplitude modulation equalization optimization method, comprising:

determining, by a Basic Input/Output System (BIOS), an effective equalization tap number that is indicative of a number of equalization taps that each provide an equalization result above a predetermined amount;

determining, by the BIOS, whether the effective equalization tap number is greater than a predetermined fraction of an available equalization tap number, wherein the available equalization tap number is indicative of a number of equalization taps that are available for equalizing a signal;

causing, by the BIOS when the effective equalization tap number is greater than the predetermined fraction of the available equalization tap number, a modulation subsystem to perform per-symbol equalization on signals modulated using Pulse Amplitude Modulation (PAM); and

causing, by the BIOS when the effective equalization tap number is not greater than the predetermined fraction of the available equalization tap number, the modulation subsystem to perform per-bit equalization on signals modulated using PAM.

15. The method of claim 14 , wherein the signals are modulated using four level PAM (PAM4).

16. The method of claim 14 , wherein the equalization is Feed Forward Equalization (FFE).

17. The method of claim 14 , wherein the equalization result that is above the predetermined amount includes an equalized signal change that is greater or equal to one percent.

18. The method of claim 14 , wherein the predetermined fraction of the available equalization tap number is half the available equalization tap number.

19. The method of claim 14 , further comprising:

performing, by the BIOS, link training operations in a pre-boot environment; and

completing, by the BIOS, the link training operations prior to determining the effective equalization tap number in the pre-boot environment.

20. The method of claim 14 , further comprising:

performing, by the BIOS, link training operations in a runtime environment; and

completing, by the BIOS, the link training operations prior to determining the effective equalization tap number in the runtime environment.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (046366/0014) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060450/0306 →
RELEASE OF SECURITY INTEREST AT REEL 046286 FRAME 0653 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058298/0093 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 046286/0653 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 046366/0014 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2018
From: CHANDRA, UMESH; MUTNURY, BHYRAV M.; CHADA, ARUN REDDY; DENG, HAN
To: DELL PRODUCTS L.P.
Reel/Frame 045023/0518 →