Non-volatile memory device and error compensation method for verifying the same

1. A non-volatile memory device, comprising:

a memory block, having a plurality of memory cells, wherein control terminals of a part of the memory cells are connected to each other, and source electrodes of the part of the memory cells are connected to each other;

a word line driver, providing a verification voltage to the memory cells;

a bit line circuit, coupled to a bit line of the memory cells, and configured to read the memory cells; and

a controller, wherein after the word line driver and the bit line circuit perform a first programming process and a first verification process on the memory cells, the controller respectively applies a preset voltage to the control terminals of the memory cells according to a programming pattern by using the word line driver, reads data from the memory cells by using the bit line circuit, and determines whether the data of each of the memory cells is normal based on the data read from the memory cells, and

when the data of specific memory cells in the memory cells is not normal, the controller performs a second programming process to the specific memory cells.

2. The non-volatile memory device as claimed in claim 1 , further comprising:

a first buffer, configured to record the programming pattern.

3. The non-volatile memory device as claimed in claim 1 , wherein the bit line circuit comprises a mask buffer configured to record masked memory cells not requiring a programming process,

wherein the controller does not determine normality of data of the masked memory cells.

4. The non-volatile memory device as claimed in claim 1 , wherein when data of the memory cells is normal, the controller completes a programming process on the memory block.

5. The non-volatile memory device as claimed in claim 1 , wherein the bit line circuit comprises a page buffer configured to record positions of the specific memory cells.

6. An error compensation method for verifying a non-volatile memory device, wherein the non-volatile memory device comprises a memory block comprising a plurality of memory cells, control terminals of a part of the memory cells are connected to each other, and source electrodes of the part of the memory cells are connected to each other, the error compensation method comprising:

after a first programming process and a first verification process are performed on the memory cells, respectively applying a preset voltage to the control terminals of the memory cells according to a programming pattern;

reading data from the memory cells;

determining whether the data of each of the memory cells is normal or not based on the data read from the memory cells; and

when data of specific memory cells is not normal, performing a second programming process to the specific memory cells.

7. The error compensation method for verifying the non-volatile memory device as claimed in claim 6 , further comprising:

recording the programming pattern through a first buffer.

8. The error compensation method for verifying the non-volatile memory device as claimed in claim 6 , further comprising:

recording positions of the specific memory cells through a page buffer.

9. The error compensation method for verifying the non-volatile memory device as claimed in claim 6 , further comprising:

recording masked memory cells not requiring a programming process through a mask buffer; and

not determining normality of data of the masked memory cells.

10. The error compensation method for verifying the non-volatile memory device as claimed in claim 6 , further comprising:

when data of the memory cells is normal, completing a programming process on the memory block.