Capacitive micromachined ultrasonic transducers (CMUTs) and related apparatus and methods
Processes for fabricating capacitive micromachined ultrasonic transducers (CMUTs) are described, as are CMUTs of various doping configurations. An insulating layer separating conductive layers of a CMUT may be formed by forming the layer on a lightly doped epitaxial semiconductor layer. Dopants may be diffused from a semiconductor substrate into the epitaxial semiconductor layer, without diffusing into the insulating layer. CMUTs with different configurations of N-type and P-type doping are also described.
1. A capacitive micromachined ultrasonic transducer (CMUT), comprising:
a membrane configured to vibrate, the membrane comprising:
a doped substrate; and
an epitaxial silicon layer disposed on the doped substrate;
a substrate separated from the epitaxial silicon layer by a cavity, and wherein the epitaxial silicon layer is disposed between the doped substrate of the membrane and the substrate; and
a dielectric layer disposed between the epitaxial silicon layer and the substrate, wherein the dielectric layer is etched to include at least one bump, and
wherein, when the CMUT is operating in a collapse mode, the dielectric layer is configured to make contact with a bottom boundary of the cavity.
2. The CMUT of claim 1 , wherein the epitaxial silicon layer is doped, and wherein the dielectric layer has a lower doping concentration than the doped substrate.
3. The CMUT of claim 2 , wherein the dielectric layer is silicon oxide.
4. The CMUT of claim 3 , wherein, when the CMUT is operating in a first mode, the dielectric layer is configured to not make contact with the bottom boundary of the cavity.
5. The CMUT of claim 4 , wherein, when the CMUT is operating in the first mode, the dielectric layer is configured to flex with the membrane.
6. A capacitive micromachined ultrasonic transducer (CMUT), comprising:
a membrane configured to vibrate, the membrane comprising:
a doped substrate; and
an epitaxial silicon layer disposed on the doped substrate;
a substrate separated from the epitaxial silicon layer by a cavity, and wherein the epitaxial silicon layer is disposed between the doped substrate of the membrane and the substrate;
a dielectric layer disposed between the epitaxial silicon layer and the substrate; and
an oxide layer disposed between the substrate and the dielectric layer, wherein the oxide layer is etched to include at least one bump,
wherein the cavity is disposed in the oxide layer,
wherein, when the CMUT is operating in a collapse mode, the dielectric layer is configured to make contact with a bottom boundary of the cavity disposed in the oxide layer, and, when the CMUT is operating in the collapse mode, the dielectric layer is configured to make contact with the at least one bump of the oxide layer.
7. The CMUT of claim 6 , wherein the dielectric layer is etched to include at least one bump and, when the CMUT is operating in the collapse mode, the at least one bump of the dielectric layer is configured to make contact with the at least one bump of the oxide layer.