Semiconductor storage device

1. A semiconductor storage device comprising:

a semiconductor substrate;

a plurality of word lines each extending in a first direction and a second direction, and being stacked in a third direction, wherein the first direction, the second direction, and the third direction cross one another, and the third direction is perpendicular to a surface of the semiconductor substrate;

a memory cell array above the semiconductor substrate and including:

first and second memory strings each including a plurality of memory cells that are connected to the word lines, respectively, and

a source line wiring layer between the semiconductor substrate and each of the first and second memory strings in the third direction,

a first bit line above the memory cell array, extending in the first direction, and connected to the first memory string;

a second bit line above the memory cell array, extending in the first direction, and connected to the second memory string;

a hookup circuit between the semiconductor substrate and the memory cell array in the third direction, and includes

a first wiring connected to the first bit line and extending in the third direction to a location that is at a lower level than the memory cell array,

a first circuit connected to the first wiring,

a second wiring connected to the second bit line and extending in the third direction to a location that is at a lower level than the memory cell array, and

a second circuit connected to the second wiring;

a first circuit group that includes a first sense amplifier circuit connected to the first circuit and a first data register connected to the first sense amplifier circuit via a first data bus; and

a second circuit group that includes a second sense amplifier circuit connected to the second circuit and a second data register connected to the second sense amplifier circuit via a second data bus

wherein the first data register, the first sense amplifier circuit, the hookup circuit, the second sense amplifier circuit, and the second data register are arranged in sequence along the first direction.

2. The semiconductor storage device according to claim 1 , wherein

a distance between the first sense amplifier circuit and the hookup circuit in the first direction and a distance between the second sense amplifier circuit and the hookup circuit in the first direction are the same, and

a distance between the first data register and the hookup circuit in the first direction and a distance between the second data register and the hookup circuit in the first direction are the same.

3. The semiconductor storage device according to claim 1 , further comprising:

a first switch circuit that connects the first sense amplifier circuit to the first data bus; and

a second switch circuit that connects the second sense amplifier circuit to the second data bus.

4. The semiconductor storage device according to claim 1 , further comprising:

a first lower bit line below the memory cell array, extending in the first direction, and connected to the first bit line via the first wiring, and

a second lower bit line below the memory cell array, extending in the first direction, and connected to the second bit line via the second wiring.

5. The semiconductor storage device according to claim 4 ,

wherein the first wiring and the second wiring are not aligned with each other when viewed along the second direction.

6. A semiconductor storage device comprising:

a semiconductor substrate;

a plurality of word lines each extending in a first direction and a second direction, and being stacked in a third direction, wherein the first direction, the second direction, and the third direction cross one another, and the third direction is perpendicular to a surface of the semiconductor substrate;

a memory cell array above the semiconductor substrate and including:

first, second, third, and fourth memory strings each including a plurality of memory cells that are connected to the word lines, respectively, and

a source line wiring layer between the semiconductor substrate and each of the first, second, third, and fourth memory strings in the third direction,

a first bit line above the memory cell array, extending in the first direction, and connected to the first memory string;

a second bit line above the memory cell array, extending in the first direction, and connected to the second memory string;

a third bit line above the memory cell array, extending in the first direction, and connected to the third memory string;

a fourth bit line above the memory cell array, extending in the first direction, and connected to the fourth memory string;

a hookup circuit between the semiconductor substrate and the memory cell array in the third direction, and includes

first, second, third, and fourth wirings connected respectively to the first, second, third, and fourth bit lines and extending in the third direction to locations that are at a lower level than the memory cell array, and

first, second, third, and fourth circuits connected respectively to the first, second, third, and fourth wirings;

a first circuit group that includes a first sense amplifier circuit connected to the first circuit, a first data register connected to the first sense amplifier circuit via a first data bus, a second sense amplifier circuit connected to the second circuit, and a second data register connected to the second sense amplifier circuit via a second data bus; and

a second circuit group that includes a third sense amplifier circuit connected to the third circuit, a third data register connected to the third sense amplifier circuit via a third data bus, a fourth sense amplifier circuit connected to the fourth circuit, and a fourth data register connected to the fourth sense amplifier circuit via a fourth data bus

wherein the second data register, the first data register, the second sense amplifier circuit, the first sense amplifier circuit, the hookup circuit, the third sense amplifier circuit, the fourth sense amplifier circuit, the third data register, and the fourth data register are arranged in sequence along the first direction.

7. The semiconductor storage device according to claim 6 ,

wherein

a distance between the first sense amplifier circuit and the hookup circuit in the first direction and a distance between the third sense amplifier circuit and the hookup circuit in the first direction are the same, and a distance between the second sense amplifier circuit and the hookup circuit in the first direction and a distance between the fourth sense amplifier circuit and the hookup circuit in the first direction are the same,

a distance between the first data register and the hookup circuit in the first direction and a distance between the third data register and the hookup circuit in the first direction are the same, and a distance between the second data register and the hookup circuit in the first direction and a distance between the fourth data register and the hookup circuit in the first direction are the same.

8. The semiconductor storage device according to claim 6 , further comprising:

a first switch circuit that connects the first sense amplifier circuit to the first data bus;

a second switch circuit that connects the second sense amplifier circuit to the second data bus;

a third switch circuit that connects the first sense amplifier circuit to the third data bus; and

a fourth switch circuit that connects the second sense amplifier circuit to the fourth data bus.

9. The semiconductor storage device according to claim 6 , further comprising first, second, third, and fourth lower bit lines below the memory cell array, extending in the first direction, and connected respectively to the first, second, third, and fourth bit lines via the first, second, third, and fourth wirings, respectively.

10. The semiconductor storage device according to claim 9 ,

wherein the first and third wirings are not aligned when viewed in the second direction, and the second and fourth wirings are not aligned when viewed in the second direction.

11. The semiconductor storage device according to claim 6 , wherein the third bit line is between the first and second bit lines, and the second bit line is between the third and fourth bit lines.