IP Library Granted Patent US 10,672,706
Granted Patent B2
US 10,672,706 · App. 15/906,536 · Granted Jun 2, 2020

Semiconductor device

Inventor: Yoshitaka Kimura (Chiba, JP)
Assignee: ABLIC INC.
H01L23/5258H01L21/76894H01L23/5226H01L23/53238H01L23/53266
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Quick Facts
Patent No.
US 10,672,706
App. No.
15/906,536
Granted
Jun 2, 2020
Kind
B2
Abstract

A semiconductor device includes a multilayer wiring structure on a substrate. The multilayer wiring structure includes: a top wiring; a fuse element, which is located on a lower layer-side of the top wiring, and is made of metal having a melting point that is higher than that of the top wiring; and a lower-layer wiring, which is connected to each of ends of the fuse element. Provided is a semiconductor device in which fuse elements made of the high-melting point metal are arranged at high density.

Claims (19)

1. A semiconductor device, comprising:

a substrate; and

a multilayer wiring structure on the substrate,

the multilayer wiring structure comprising:

a top wiring;

a fuse element located on a lower-layer side of the top wiring, the fuse element comprising a first layer of a first metal and a second layer of a second metal disposed directly on top of the first layer, the second layer being thicker than the first layer, the first metal and the second metal having a melting point that is higher than a melting point of the top wiring; and

a lower-layer wiring connected to each of both ends of the first layer of the fuse element.

2. The semiconductor device according to claim 1 , wherein the lower-layer wiring is connected directly to each of the both ends from a lower-layer side of the fuse element.

3. The semiconductor device according to claim 1 , wherein the fuse element has a thickness of 200 nm or more and 1,000 nm or less.

4. The semiconductor device according to claim 2 , wherein the fuse element has a thickness of 200 nm or more and 1,000 nm or less.

5. The semiconductor device according to claim 1 , wherein the lower-layer wiring is connected to each of the both ends of the fuse element through a via.

6. The semiconductor device according to claim 3 , wherein the lower-layer wiring is connected to each of the both ends of the fuse element through a via.

7. A semiconductor device, comprising:

a substrate; and

a multilayer wiring structure on the substrate,

the multilayer wiring structure comprising:

a top wiring;

a fuse element made from the top wiring, the fuse element comprising a first layer of a first metal and a second layer of a second metal disposed directly on top of the first layer, the second layer being thicker than the first layer, the first metal and the second metal having a melting point that is higher than a melting point of the top wiring; and

a lower-layer wiring connected to each of both ends of the first layer of the fuse element through a via.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2018
From: KIMURA, YOSHITAKA
To: ABLIC INC.
Reel/Frame 045054/0135 →
Priority Claims (1)
JP 2017-043157 · Mar 7, 2017 · national
Continuity (1)
Related Publication 20180261541A1 · Sep 13, 2018