IP Library Granted Patent US 10,698,696
Granted Patent B2
US 10,698,696 · App. 15/910,831 · Granted Jun 30, 2020

Chipset fuse programming system

Inventors: Jayanth Raghuram (Round Rock, TX); Rui Shi (Cedar Park, TX); Ching-Lung Chao (Austin, TX)
Assignee: Dell Products L.P.
G06F9/441G06F1/24
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Quick Facts
Patent No.
US 10,698,696
App. No.
15/910,831
Granted
Jun 30, 2020
Kind
B2
Abstract

A chipset fuse programming system includes a chassis that houses a chipset with programmable fuses and a Basic Input/Output System (BIOS) that is coupled to the chipset. The BIOS includes a BIOS storage storing fuse configuration profiles. The BIOS determines a chipset type of the chipset and selects a first fuse configuration profile based on the chipset type. The BIOS then programs the programmable fuses included in the chipset using the first fuse configuration profile. A central processing system may be housed in the chassis and coupled to the BIOS, with the BIOS determining a central processing system type of the central processing system, and selecting the first fuse configuration profile based on a combination of the chipset type and the central processing system type.

Claims (55)

1. A chipset fuse programming system, comprising:

a chassis;

a chipset that is located in the chassis and that includes a plurality of programmable fuses; and

a Basic Input/Output System (BIOS) that is located in the chassis and coupled to the chipset, wherein the BIOS includes a BIOS storage including a plurality of fuse configuration profiles, and wherein the BIOS is configured to:

determine a chipset type of the chipset;

select, based on the chipset type of the chipset, a first fuse configuration profile of the plurality of fuse configuration profiles; and

program, using the first fuse configuration profile, the plurality of programmable fuses included in the chipset.

2. The system of claim 1 , wherein the chipset type is one of a pre-production chipset type and a production chipset type.

3. The system of claim 1 , further comprising:

a central processing system that is located in the chassis and coupled to the BIOS, wherein the BIOS is configured to:

determine a central processing system type of the central processing system; and

select the first fuse configuration profile based on a combination of the chipset type of the chipset and the central processing system type of the central processing system.

4. The system of claim 3 , wherein the central processing system type is one of a pre-production central processing system type and a production central processing system type.

5. The system of claim 1 , wherein the plurality of fuse configuration profiles include a default fuse configuration profile, and wherein the selecting the first fuse configuration profile and using the first fuse configuration profile to program the plurality of programmable fuses includes:

erasing the default fuse configuration profile from a first region of the BIOS storage; and

writing the first fuse configuration profile to the first region of the BIOS storage.

6. The system of claim 1 , wherein the first fuse configuration profile provides for the programming of the programmable fuses such that the chipset includes at least one of:

public key information; and

feature information for enabling at least one computing device feature.

7. An Information Handling System (IHS), comprising:

a processing subsystem; and

a memory subsystem that is coupled to the processing subsystem and that includes instructions that, when executed by the processing subsystem, causes the processing subsystem to provide a Basic Input/Output System (BIOS) that is configured to:

determine a chipset type of a chipset that is coupled to the BIOS;

select, based on the chipset type of the chipset, a first fuse configuration profile of a plurality of fuse configuration profiles that are included in a BIOS storage; and

program, using the first fuse configuration profile, a plurality of programmable fuses that are included in the chipset.

8. The IHS of claim 7 , wherein the chipset type is one of a pre-production chipset type and a production chipset type.

9. The IHS of claim 7 , wherein the BIOS is configured to:

determine a central processing system type of a central processing system that is coupled to the BIOS; and

select the first fuse configuration profile based on a combination of the chipset type of the chipset and the central processing system type of the central processing system.

10. The IHS of claim 9 , wherein the central processing system type is one of a pre-production central processing system type and a production central processing system type.

11. The IHS of claim 7 , wherein the plurality of fuse configuration profiles include a default fuse configuration profile, and wherein the selecting the first fuse configuration profile and using the first fuse configuration profile to program the plurality of programmable fuses includes:

erasing the default fuse configuration profile from a first region of the BIOS storage; and

writing the first fuse configuration profile to the first region of the BIOS storage.

12. The IHS of claim 11 , wherein the BIOS is configured to:

cause a reset of the IHS following the writing of the first fuse configuration profile to the first region of the BIOS storage, wherein the programming of the plurality of programmable fuses using the first fuse configuration profile is performed following the reset.

13. The IHS of claim 7 , wherein the first fuse configuration profile provides for the programming of the programmable fuses such that the chipset includes at least one of:

public key information; and

feature information for enabling at least one IHS feature.

14. A method for programming chipset fuses, comprising:

determining, by a Basic Input/Output System (BIOS), a chipset type of a chipset that is coupled to the BIOS;

selecting, by the BIOS based on the chipset type of the chipset, a first fuse configuration profile of a plurality of fuse configuration profiles that are included in a BIOS storage; and

programming, by the BIOS using the first fuse configuration profile, a plurality of programmable fuses that are included in the chipset.

15. The method of claim 14 , wherein the chipset type is one of a pre-production chipset type and a production chipset type.

16. The method of claim 14 , further comprising:

determining, by the BIOS, a central processing system type of a central processing system that is coupled to the BIOS; and

selecting, by the BIOS, the first fuse configuration profile based on a combination of the chipset type of the chipset and the central processing system type of the central processing system.

17. The method of claim 16 , wherein the central processing system type is one of a pre-production central processing system type and a production central processing system type.

18. The method of claim 14 , wherein the plurality of fuse configuration profiles include a default fuse configuration profile, and wherein the selecting the first fuse configuration profile and using the first fuse configuration profile to program the plurality of programmable fuses includes:

erasing the default fuse configuration profile from a first region of the BIOS storage; and

writing the first fuse configuration profile to the first region of the BIOS storage.

19. The method of claim 18 , further comprising:

causing, by the BIOS, a reset of a computing device that includes the BIOS following the writing of the first fuse configuration profile to the first region of the BIOS storage, wherein the programming of the plurality of programmable fuses using the first fuse configuration profile is performed following the reset.

20. The method of claim 14 , wherein the first fuse configuration profile provides for the programming of the programmable fuses such that the chipset includes at least one of:

public key information; and

feature information for enabling at least one feature in a computing device that includes the BIOS.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (046366/0014) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060450/0306 →
RELEASE OF SECURITY INTEREST AT REEL 046286 FRAME 0653 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058298/0093 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 046366/0014 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 046286/0653 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2018
From: RAGHURAM, JAYANTH; SHI, RUI; CHAO, CHING-LUNG
To: DELL PRODUCTS L.P.
Reel/Frame 045094/0212 →
Cited By (1)
US 12,693,797