IP Library Granted Patent US 10,170,435
Granted Patent B2
US 10,170,435 · App. 15/911,414 · Granted Jan 1, 2019

Guard ring structure and method for forming the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,170,435
App. No.
15/911,414
Granted
Jan 1, 2019
Kind
B2
Abstract

A method for forming a seal ring structure provides a semiconductor substrate having a first doping region formed over a top portion thereof. The method forms a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers has a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions, and then performs an etching process to a first doping region of the substrate. The method then removes the first doping region not covered by the patterned photoresist layers and forms a plurality of patterned first doping regions. The method then removes the patterned photoresist layers and forms an isolation region between and adjacent to the patterned first doping regions. Finally, the method forms a plurality of interconnect elements over the semiconductor substrate.

Claims (20)

1. A method for forming a seal ring structure, comprising:

providing a semiconductor substrate having a first doping region formed over a top portion thereof, wherein the semiconductor substrate has a first dopant type and the first doping region has the first dopant type or a second dopant type opposite to the first dopant type;

forming a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers comprises a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions and extending along a second direction perpendicular to the first direction;

performing an etching process to the first doping region using the patterned photoresist layers as an etching mask, removing the first doping region not covered by the patterned photoresist layers and forming a plurality of patterned first doping regions, wherein each of the patterned first doping regions comprises a plurality of parallel strip portions extending along the first direction and a plurality of bridge portions formed between the parallel strip portions and extending along the second direction perpendicular to the first direction;

removing the patterned photoresist layers;

forming an isolation region between and adjacent to the patterned first doping regions; and

forming a plurality of interconnect elements over the semiconductor substrate, respectively covering one of the patterned first doping regions thereunder.

2. The method as claimed in claim 1 , further comprising a plurality of first well regions embedded in the semiconductor and respectively underlying one of the patterned first doping regions, wherein the first well regions have the second dopant type and the first doping regions have the first dopant type.

3. The method as claimed in claim 2 , further comprising a plurality of second well regions embedded in the semiconductor and respectively adjacent to one of the first well regions, wherein the second well regions have the first dopant type and the first doping regions have the first dopant type.

4. The method as claimed in claim 2 , wherein the first dopant type is p-type and the second dopant type is n-type.

5. A method for forming a seal ring structure, comprising:

providing a semiconductor substrate having a first doping region formed over a top portion thereof, wherein the semiconductor substrate has a first dopant type and the first doping region has the first dopant type or a second dopant type opposite to the first dopant type;

forming a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers comprises a plurality of parallel strip portions extending along a first direction and a plurality of arm portions extending from opposite sides of each of the parallel strip portions along a second direction perpendicular to the first direction;

performing an etching process to the first doping region using the patterned photoresist layers as an etching mask, removing the first doping region not covered by the patterned photoresist layers and forming a plurality of patterned first doping regions, wherein each of the patterned first doping regions comprises a plurality of parallel strip portions extending along the first direction and a plurality of arm portions formed between the parallel strip portions and extending along the second direction perpendicular to the first direction;

removing the patterned photoresist layers;

forming an isolation region between and adjacent to the patterned first doping regions; and

forming a plurality of interconnect elements over the semiconductor substrate, respectively covering one of the patterned first doping regions thereunder.

6. The method as claimed in claim 5 , further comprising a plurality of first well regions embedded in the semiconductor and respectively underlying one of the patterned first doping regions, wherein the first well regions have the second dopant type and the first doping regions have the first dopant type.

7. The method as claimed in claim 5 , further comprising a plurality of second well regions embedded in the semiconductor and respectively adjacent to one of the first well regions, wherein the second well regions have the first dopant type and the first doping regions have the first dopant type.

8. The method as claimed in claim 5 , wherein the first dopant type is p-type and the second dopant type is n-type.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 060646 FRAME: 0916. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 23, 2022
From: FORTIETH FLOOR, LLC
To: HAMILCAR BARCA IP LLC
Reel/Frame 061301/0567 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2022
From: FORTIETH FLOOR, LLC
To: HANNIBAL BARCA IP LLC
Reel/Frame 060646/0916 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2021
From: MEDIATEK SINGAPORE PTE LTD.
To: FORTIETH FLOOR LLC
Reel/Frame 058342/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2018
From: LU, CHIYUAN; LIN, CHIEN-CHIH; HUNG, CHENG-CHOU; HUANG, YU-HUA
To: MEDIATEK SINGAPORE PTE. LTD
Reel/Frame 045104/0455 →
Cited By (1)
US 12,419,105