Modular control in a quantum computing system
In a general aspect, a quantum computing method is described. In some aspects, a control system in a quantum computing system assigns subsets of qubit devices in a quantum processor to respective cores. The control system identifies boundary qubit devices residing between the cores in the quantum processor and generates control sequences for each respective core. A signal delivery system in communication with the control system and the quantum processor receives control signals to execute the control sequences, and the control signals are applied to the respective cores in the quantum processor.
1. A quantum computing method comprising:
assigning, by operation of a control system in a quantum computing system, subsets of qubit devices in a quantum processor to respective cores, each subset of qubit devices comprising multiple qubit devices;
identifying, by operation of the control system, boundary qubit devices residing between the cores in the quantum processor;
generating, by operation of the control system, control sequences for each respective core, wherein the control sequences are configured to apply an identity operation to the boundary qubit devices;
delivering to the quantum processor, by operation of a signal delivery system in communication with the control system and the quantum processor, control signals to execute the control sequences; and
applying the control signals to the respective cores in the quantum processor.
2. The method of claim 1 , wherein each of the cores comprises a respective subset of qubit devices and additional quantum circuit devices.
3. The method of claim 2 , wherein the additional quantum circuit devices comprise coupler devices.
4. The method of claim 1 , wherein the control sequences comprise first control sequences, and the method further comprises:
receiving, by operation of the signal delivery system, from the quantum processor, qubit readout signals from the cores; and
generating, by operation of the control system, second control sequences based on the qubit readout signals.
5. The method of claim 1 , wherein generating the control sequences comprises:
determining an identity error syndrome for one or more of the boundary qubit devices;
evaluating a cost function based on the identity error syndrome; and
generating a control sequence based on a minimization of the cost function.
6. The method of claim 1 , wherein applying the control signals to the respective cores in the quantum processor comprises applying the control signals to two or more of the cores in the quantum processor in parallel.
7. The method of claim 1 , wherein applying the control signals to the respective cores in the quantum processor comprises applying the control signals to two or more of the cores in the quantum processor in series.
8. The method of claim 1 , wherein the method further comprises identifying instruction sets for the respective cores, wherein the control sequence for each core is generated from the instruction set for that core.
9. The method of claim 8 , wherein the instruction set for each core comprises a unitary operator defined over a Hilbert space defined by the qubit devices assigned to that core.
10. The method of claim 8 , wherein the instruction set for each core comprises a sequence of quantum logic gates for application to the qubit devices assigned to that core.
11. The method of claim 1 , wherein the cores comprise a first set of cores, and the method further comprises, by operation of the control system, reassigning the qubit devices from the first set of cores to define a second, distinct set of cores.
12. A quantum computing system comprising:
a quantum processor comprising an array of qubit devices;
a control system configured to perform operations comprising:
assigning subsets of the qubit devices to respective cores, each subset of qubit devices comprising multiple qubit devices;
identifying boundary qubit devices residing between the cores in the quantum processor; and
generating control sequences for each respective core, wherein the control sequences are configured to apply an identity operation to the boundary qubit devices; and
a signal delivery system in communication with the control system and the quantum processor, the signal delivery system configured to:
receive, from the control system, control signals to execute the control sequences; and
deliver the control signals to the quantum processor for application to the respective cores.
13. The system of claim 12 , wherein each of the cores comprises a respective subset of the qubit devices and additional quantum circuit devices.
14. The system of claim 13 , wherein the additional quantum circuit devices comprise coupler devices.
15. The system of claim 12 , wherein the control sequences comprise first control sequences, and:
the signal delivery system is further configured to receive, from the quantum processor, qubit readout signals from the cores; and
the control system is further configured to generate second control sequences based on the qubit readout signals.
16. The system of claim 12 , wherein the control system is further configured to perform operations comprising:
determining an identity error syndrome for one or more of the boundary qubit devices;
evaluating a cost function based on the identity error syndrome; and
generating a control sequence based on a minimization of the cost function.
17. The system of claim 12 , wherein the quantum processor is configured to apply the control signals to two or more of the cores in the quantum processor in parallel.
18. The system of claim 12 , wherein the quantum processor is configured to apply the control signals to two or more of the cores in the quantum processor in series.
19. The system of claim 12 , wherein the control system is configured to perform operations further comprising identifying instruction sets for the respective cores, wherein the control sequence for each core is generated from the instruction set for that core.
20. The system of claim 19 , wherein the instruction set for each core comprises a unitary operator defined over a Hilbert space defined by the qubit devices assigned to that core.
21. The system of claim 19 , wherein the instruction set for each core comprises a sequence of quantum logic gates for application to the qubit devices assigned to that core.
22. The system of claim 12 , wherein the cores comprise first cores and wherein the control system is further configured to perform operations comprising: reassigning the subsets of qubit devices in the quantum processor to respective second cores.