Semiconductor device and method of manufacturing a semiconductor device

1. A semiconductor flash memory device comprising a strained semiconductor layer, a charge trapping layer, and a contact etch stop layer, CESL,

wherein the CESL comprises a silicon oxynitride contact etch stop layer having a refractive index in the range from 1.65 to 1.80,

wherein the CESL forms part of a dual stress liner having both compressive and tensile strain regions, and

wherein the strained semiconductor layer forms part of a strained silicon directly on insulator, SSOI, layer.

2. The semiconductor flash memory device according to claim 1 , wherein the SSOI layer is substantially SiGe-free.

3. The semiconductor flash memory device according to claim 1 , wherein the thickness of the strained semiconductor layer is in the range from 20 nm to 50 nm.

4. The semiconductor flash memory device according to claim 1 , further comprising a deep trench isolation, DTI, region provided within the SSOI layer.

5. The semiconductor flash memory device according to claim 1 , wherein the memory device is a SONOS memory device and the charge trapping layer is a silicon nitride or silicon oxynitride layer forming part of an ONO stack.

6. The semiconductor flash memory device according to claim 1 , wherein the memory device is a floating gate flash memory device and the charge trapping layer is the floating gate.

7. The semiconductor flash memory device according to claim 6 , wherein the floating gate is formed of polysilicon.

8. The semiconductor flash memory device according to claim 1 , wherein the CESL is strained.

9. The semiconductor flash memory device according to claim 1 , wherein the thickness of the CESL is in the range from 300 Å to 500 Å.

10. The semiconductor flash memory device according to claim 1 , wherein the thickness of the CESL is substantially 400 Å.

11. The semiconductor flash memory device according to claim 1 , wherein the refractive index of the CESL is substantially 1.72.

12. A method for use in fabricating a semiconductor flash memory device according to claim 1 , the method comprising:

providing a substrate having thereon the strained silicon on insulator, SSOI, layer;

forming a tunnel oxide layer on the SSOI layer;

forming a charge trapping layer on the tunnel oxide layer;

forming a polysilicon layer above the charge trapping layer; and

depositing a suicide layer and the contact etch stop layer, CESL, on the polysilicon layer,

wherein the CESL comprises a silicon oxynitride contact etch stop layer wherein parameters of the CESL deposition are chosen to result in the silicon oxynitride contact etch stop layer having a refractive index in the range from 1.65 to 1.80,

wherein the CESL forms part of a dual stress liner having both compressive and tensile strain regions, and

wherein the strained semiconductor layer forms part of a strained silicon directly on insulator, SSOI, layer.

13. The method according to claim 12 , wherein the semiconductor flash memory device is a SONOS memory device and the charge trapping layer is a silicon oxynitride or silicon nitride layer forming part of an ONO stack, wherein the method further comprises:

forming the top oxide layer of the ONO stack by re-oxidizing part of the silicon oxynitride or silicon nitride layer of the stack by a low-temperature plasma oxidation process.

14. The method according to claim 12 , wherein the tunnel oxide layer is formed by a low-temperature plasma oxidation process.

15. The method according to claim 13 , wherein the temperature of the low-temperature plasma oxidation process is less than or equal to 400 degrees Celsius.

16. The method according to claim 12 , further comprising forming one or more deep trench isolation, DTI, regions within the SSOI layer.

17. The method according to claim 12 , wherein parameters of the CESL deposition are chosen to result in a CESL having a refractive index of substantially 1.72.

18. The semiconductor flash memory device according to claim 1 , wherein the strained semiconductor layer and the CESL are both formed so as to reduce the probability of an electron tunnelling out of the charge trapping layer.