Semiconductor device
To provide a semiconductor device capable of easily testing a built-in self-test control circuit itself, the semiconductor device has: a test pattern generator; an output response analyzer configured to compare an expected value to a test result of a circuit; a plurality of test control circuits each configured to control the test pattern generator and the output response analyzer; and a circuit under test. The semiconductor device has: a first test mode in which a first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test; and a second test mode in which the test control circuit other than the first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test.
1. A semiconductor device, comprising:
a test pattern generator configured to generate a test pattern;
a circuit under test configured to output, in response to the supply of the test pattern from the test pattern generator, a test result in accordance with the test pattern,
an output response analyzer configured to compare an expected value to the test result; and
a plurality of test control circuits configured to control the test pattern generator and the output response analyzer;
the semiconductor device having:
a first test mode in which a first test control circuit of the plurality of test control circuits controls the test pattern generator and the output response analyzer to cause the test pattern to be supplied to a test control circuit of the plurality of test control circuits other than the first test control circuit, to thereby perform a test; and
a second test mode in which a second test control circuit different from the first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern to be supplied to the first test control circuit, to thereby perform a test.
2. A semiconductor device according to claim 1 , further comprising:
a second circuit under test;
a second test pattern generator configured to generate a second test pattern to be supplied to the second circuit under test; and
a second output response analyzer configured to compare an expected value to a test result of the second circuit under test, the test result being obtained as a result of supply of the second test pattern generated by the second test pattern generator to the second circuit under test,
the first test control circuit being configured to perform a test in the first test mode by controlling the second test pattern generator and the second output response analyzer to cause the second test pattern to be supplied to the second circuit under test,
a second test control circuit different from the first test control circuit being configured to perform a test in the second test mode by controlling the second test pattern generator and the second output response analyzer to cause the second test pattern to be supplied to the second circuit under test.