Ultra-low power magnetoelectric magnetic field sensor

1. A method for making an on-chip micro-resonator magnetic sensor, comprising:

depositing a low-stress thermal nitride on a top side and a bottom side of a wafer;

depositing a bottom contact serving as a seed layer for a piezoelectric on the low-stress thermal nitride on the top side of the wafer;

depositing a piezoelectric layer on the bottom contact serving as a seed layer;

patterning a first photoresist or lift-off layer to define a geometry for a beam on the piezoelectric layer;

applying a metallic buffer layer to the piezoelectric layer and the patterned photoresist or lift-off layer;

applying a magnetostrictive layer to the piezoelectric layer and the patterned photoresist or lift-off layer;

removing the portion of the magnetostrictive layer from the patterned photoresist or lift-off layer;

patterning a second photoresist layer on the piezoelectric layer for a first electrode;

etching the piezoelectric layer to define the first electrode;

patterning a third photoresist layer on the magnetostrictive layer for a second electrode;

metallizing the first and second electrodes;

performing a chemical lift off process to define the first electrode;

patterning a fourth photoresist layer of expanded openings on the low-stress thermal nitride on the bottom side of the wafer;

etching openings in the low-stress thermal nitride on the bottom side of the wafer to form windows to the wafer;

forming a smaller opening at the top side of the wafer; and

performing a bottom side RIE etch on the low-stress thermal nitride to release a multi-layer beam;

resulting in a magnetoelectric micro-beam resonator that generates a magnetically driven resonance shift.

2. The method of claim 1 , wherein the bottom contact serving as a seed layer comprises Pt, Hf, Ta, or any combination thereof.

3. The method of claim 1 , wherein the low-stress thermal nitride comprises low-stress LPCVD silicon nitride, low-stress CVD silicon nitride, low-stress PECVD silicon nitride, or low-stress ALD silicon nitride.

4. The method of claim 1 , wherein the low-stress thermal nitride has a tensile stress in the range of 0-100 MPa.

5. The method of claim 1 , wherein the low-stress thermal nitride comprises silicon nitride.

6. The method of claim 5 , wherein the forming a smaller opening at the top side of the wafer comprises opening windows in the silicon nitride by CF 4 plasma followed by isotropically etching the silicon using XeF 2 .

7. The method of claim 1 , wherein the piezoelectric layer comprises AlN, PMN-PT, BTO, or any combination thereof.

8. The method of claim 1 , wherein the magnetostrictive layer comprises, Fe, Co, Ni, FeCo, FeCoV, FeGa, or any combination thereof.

9. The method of claim 1 , wherein the magnetic sensor has a sensitivity 10 −10 Tesla/Hz 1/2 or less.

10. The method of claim 1 , wherein the magnetic sensor has a power dissipation of less than 10 mW.

11. The method of claim 1 , wherein the magnetic sensor has a power dissipation of about 0.1 mW.

12. The method of claim 1 , wherein the forming a smaller opening at the top side of the wafer comprises performing a KOH etch on the bottom side of the wafer following crystalline angles, opening windows from the top side with a CF 4 plasma, or a combination thereof.

13. The method of claim 1 , wherein the piezoelectric layer is deposited at a temperature between 450 and 550° C.