IP Library Granted Patent US 10,546,773
Granted Patent B2
US 10,546,773 · App. 15/919,652 · Granted Jan 28, 2020

Semiconductor device and semiconductor device fabrication method

Inventors: Yasunori Uchino (Kuwana, JP); Kenichi Watanabe (Kuwana, JP)
Assignee: FUJITSU SEMICONDUCTOR LIMITED
H01L21/76816G06F17/5068G06F17/5077H01L21/76802H01L21/76807H01L21/76808H01L21/76877H01L23/481H01L23/528H01L23/5226H01L2924/0002
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Quick Facts
Patent No.
US 10,546,773
App. No.
15/919,652
Filed
Mar 13, 2018
Granted
Jan 28, 2020
Kind
B2
Art Unit
2851
USPC
716/119
Abstract

A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.

Claims (28)

1. A computer-readable non-transitory storage medium storing a computer program, the computer program causing a computer to perform a process comprising:

acquiring design data that includes information of a layout of a first wiring formed in a first insulating layer, a second wiring that is formed in the first insulating layer and that is separated from the first wiring, a via that is formed in a second insulating layer over the first insulating layer and that is connected to the first wiring, and a third wiring that is formed in the second insulating layer over the first insulating layer and which is connected to the via;

extracting from the acquired design data information of a layout of the via and the third wiring; and

forming a first nick portion at an outer edge of the third wiring beside a portion of the third wiring to which the via is connected on the basis of the extracted information of the layout of the via and the third wiring, wherein

the first wiring and a first part of the second wiring overlap with the third wiring in a plan view.

2. The computer-readable non-transitory storage medium storing the computer program according to claim 1 , wherein:

the outer edge includes a first outer edge portion, a second outer edge portion that intersects the first outer edge portion, and a third outer edge portion that is opposite to the first outer edge portion and that intersects the second outer edge portion;

the forming of the first nick portion includes forming the first nick portion at the first outer edge portion of the outer edge of the third wiring;

the first nick portion is located beside the portion of the third wiring to which the via is connected;

the second outer edge portion is located opposite to the first nick portion;

the portion of the third wiring is located between the first nick portion and the second outer edge portion;

a first distance between the first nick portion and the second outer edge portion is shorter than a second distance between the first outer edge portion and the third outer edge portion.

3. The computer-readable non-transitory storage medium storing the computer program according to claim 2 , wherein the first distance is 1 μm or less.

4. The computer-readable non-transitory storage medium storing the computer program according to claim 2 , wherein the via is formed in a region within 0.1 μm from the first outer edge portion in a direction from the first outer edge portion to the third outer edge portion.

5. The computer-readable non-transitory storage medium storing the computer program according to claim 2 , wherein length of the first nick portion in a direction from the first outer edge portion to the third outer edge portion is 0.25 μm or more.

6. The computer-readable non-transitory storage medium storing the computer program according to claim 1 , wherein:

the forming of the first nick portion includes forming a second nick portion opposite the first nick portion; and

the portion of the third wiring is located between the first nick portion and the second nick portion.

7. The computer-readable non-transitory storage medium storing the computer program according to claim 6 , wherein:

the outer edge includes a first outer edge portion and a third outer edge portion opposite the first outer edge portion;

the first outer edge portion includes the first nick portion and the second nick portion; and

a third distance between the first nick portion and the second nick portion is shorter than a second distance between the first outer edge portion and the third outer edge portion.

8. The computer-readable non-transitory storage medium storing the computer program according to claim 7 , wherein the third distance is 1 μm or less.

9. The computer-readable non-transitory storage medium storing the computer program according to claim 7 , wherein the via is formed in a region within 0.1 μm from the first outer edge portion in a direction from the first outer edge portion to the third outer edge portion.

10. The computer-readable non-transitory storage medium storing the computer program according to claim 7 , wherein length of the first nick portion and length of the second nick portion in a direction from the first outer edge portion to the third outer edge portion are 0.25 μm or more.

11. The computer-readable non-transitory storage medium storing the computer program according to claim 1 , wherein the second wiring is formed adjacently to the first wiring in the first insulating layer.

12. The computer-readable non-transitory storage medium storing the computer program according to claim 1 , wherein a second part of the second wiring overlaps with the first nick portion in a plan view.

13. The computer-readable non-transitory storage medium storing the computer program according to claim 1 , wherein the first nick portion is located beside the via.

Assignments (2)
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
Priority Claims (1)
JP 2013-126269 · Jun 17, 2013 · national
Continuity (3)
Division 15152034 · May 11, 2016
Division 14293435 · Jun 2, 2014
Related Publication 20180204766A1 · Jul 19, 2018