Control module for multiple mixed-signal resources management
View Patent ↗The present solution targets independent or inter-dependent resource management scenarios such as multi-sensor and other scenarios of possible process/component sharing, intended for individual or group synchronized core task management as part of a flexible long-term solution for monitoring, self-calibration, built-in self-testing, measurements and/or group synchronization dependant strategies. An extension to I2C/I3C compatible instruments is described. Disclosed is a module comprising an interpreter sub-module, for receiving and responding to I2C/I3C sequences and a register bank module comprising a plurality of registers for storing values. The disclosed module and method of operation can be used for initialization, measurement, and resource management through mixed-signal analog bus scheduling, synchronization and group addressing for built-in calibration strategies for example.
1. A Setup, Capture, Process and Scan (SCPS) module, comprising:
an interpreter sub-module; and
a register bank module comprising:
an instruction register;
a state register;
a status register;
a group address register;
a member address register;
a write register pointer register;
a read register pointer register;
a group write pointer register;
a group read pointer register;
wherein the interpreter sub-module is configured to receive and respond to I3C (augmented inter integrated circuit sequences, supplemented with SCPS sequences, on reception of an instruction preceded by any of:
an I3C address;
a global SCPS address comprising an I3C global address call followed by a SCPS global instruction, (SGI);
a group SCPS address comprising a 10-bit I3C address followed by an 8-bit group SCPS address and by a group instruction; or
a member-specific SCPS address comprising a group SCPS address, followed by a member address and a member-specific instruction,
wherein the register bank module comprises one or more token registers.
2. The module according to claim 1 , wherein the register bank module comprises at least one user defined register.
3. The module according to claim 1 , comprising an element bank add-on SCPS handler sub-module.
4. The module according to claim 1 , wherein the SCPS global instruction (SGI) comprises:
a state instruction;
a lock instruction; or
a request instruction.
5. The module according to claim 1 , wherein the group or member-specific instruction comprises:
a setup instruction set;
a capture instruction set;
a process instruction set; or
a scan instruction set.
6. The module according to claim 1 , wherein said module is configured to implement a method of operating a setup, capture, process and scan (SPCS) module, comprising the steps of:
storing the last valid entered instruction, in the instruction register;
storing the current action state of the instruction in the state register;
storing the internal status of the SCPS module in the status register;
storing the group address of the current module in the group address register;
storing the specific address of the module within the group of the current module in the member address register;
storing the target register address to be written to in the write register pointer register;
storing the target register address to be read from in the read register pointer register;
storing the member address to be written to in the group write pointer register; and
storing the member address to be read from in the group read pointer register.
7. A mixed signal bus, comprising at least one of device comprising a setup, capture, process and scan (SCPS) module according to claim 1 , a connection to the at least one device, wherein the at least one device comprises a shared resource.
8. A method of operating a setup, capture, process and scan (SPCS) module, comprising the steps of:
executing a setup instruction by clearing, flags or registers, writing or updating registers;
executing a state instruction by modifying a state register among the registers, clearing a pointer registers among the registers, clearing internal flags and clearing a token register among the registers, if present, except a global flag if present;
executing a lock instruction by setting a lock level for the SCPS module;
executing a request instruction by coordinating use of shared resources through availability verification;
storing a last valid entered instruction, in an instruction register;
storing a current action state of the state instruction in the state register;
storing an internal status of the SCPS module in a status register;
storing a group address of the current module in a group address register;
storing a specific address of the module within a group of the current module in a member address register;
storing a target register address to be written to in a write register pointer register;
storing a target register address to be read from in a read register pointer register;
storing a member address to be written to in a group write pointer register; and
storing a member address to be read from in a group read pointer register.
9. The method of claim 8 , further comprising the step of:
storing a token space of the associated resources that have been assigned to a specific module in a token register having bits,
wherein each bit(s) of the token register represents a specific token for a specific shared resource.
10. The method according to claim 8 , comprising the steps:
executing a capture instruction by initiating multiple step sequential setups, direct accessing specific pre-arranged setups, sending setup parameters, starting a capture or ending a capture;
executing a process instruction by synchronizing inter-module actions that have no direct inter-module dependency, through the use of pre-established dependent STATES or through the use of specifiers, both at a group level or member-specific; and
executing a scan instruction by reading or transferring from registers of the addressed modules.