IP Library Granted Patent US 10,515,682
Granted Patent B2
US 10,515,682 · App. 15/924,909 · Granted Dec 24, 2019

System and method for memory fault resiliency in a server using multi-channel dynamic random access memory

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Quick Facts
Patent No.
US 10,515,682
App. No.
15/924,909
Granted
Dec 24, 2019
Kind
B2
Abstract

An on-package multi-channel dynamic random access memory stores data associated with write requests. An off-package memory stores a copy of the data associated with the write requests. A resiliency driver detects a write request, stores data for the write request to the on-package multi-channel dynamic random access memory as a primary image, stores a backup of the data for the write request to the off-package memory as a secondary image, detects a read request, and reads data for the read request from the on-package multi-channel dynamic random access memory as the primary image.

Claims (47)

1. An information handling system comprising:

an on-package multi-channel dynamic random access memory to store data associated with write requests;

an off-package memory to store a copy of the data associated with the write requests; and

a processor core of a central processing unit to communicate with the on-package multi-channel dynamic random access memory and with the off-package memory, the processor core to execute a resiliency driver, the resiliency driver to detect a write request, to store data for the write request to the on-package multi-channel dynamic random access memory as a primary image, to store a backup of the data for the write request to the off-package memory as a secondary image, to detect a read request, and to read data for the read request from the on-package multi-channel dynamic random access memory as the primary image;

wherein the resiliency driver to determine whether a persistent memory read error has occurred on the on-package multi-channel dynamic random access memory while the data for the read request is being read from the on-package multi-channel dynamic random access memory, if the persistent memory read error has occurred, the resiliency driver to read the data for the read request from the off-package memory.

2. The information handling system of claim 1 , the resiliency driver to determine whether the data read from the off-package memory is correct, if the data read from the off-package memory is correct, the resiliency driver to perform a mirror scrub to write the correct data from the off-package memory to the on-package multi-channel dynamic random access memory.

3. The information handling system of claim 2 , wherein the correct data from the off-package memory is overwritten on corrupted data of the on-package multi-channel dynamic random access memory during the mirror scrub.

4. The information handling system of claim 2 , the resiliency driver to determine whether the mirror scrub is successful, if the mirror scrub is not successful, the resiliency driver to direct future read and write request only to the off-package memory.

5. The information handling system of claim 1 , wherein the off-package memory is a dual in-line memory module in communication with the processor core.

6. The information handling system of claim 1 , wherein the on-package multi-channel dynamic random access memory is an on-chip memory for the central processing unit.

7. A method comprising:

executing, by a processor of a central processing unit, a resiliency driver to perform mirroring between an on-package multi-channel dynamic random access memory and an off-package memory;

detecting, by the resiliency driver, a write request;

storing, by the resiliency driver, data for the write request to the on-package multi-channel dynamic random access memory as a primary image;

storing, by the resiliency driver, a backup of the data for the write request to the off-package memory as a secondary image;

detecting, by the resiliency driver, a read request;

reading, by the resiliency driver, data for the read request from the on-package multi-channel dynamic random access memory as the primary image;

determining, by the resiliency driver, whether a persistent memory read error has occurred on the on-package multi-channel dynamic random access memory while the data for the read request is being read from the on-package multi-channel dynamic random access memory; and

if the persistent memory read error has occurred, reading the data for the read request from the off-package memory.

8. The method of claim 7 , further comprising:

determining, by the resiliency driver, whether the data read from the off-package memory is correct; and

if the data read from the off-package memory is correct, performing a mirror scrub to write the correct data from the off-package memory to the on-package multi-channel dynamic random access memory.

9. The method of claim 8 , wherein the correct data from the off-package memory is overwritten on corrupted data of the on-package multi-channel dynamic random access memory during the mirror scrub.

10. The method of claim 8 , further comprising:

determining, by the resiliency driver, whether the mirror scrub is successful; and

if the mirror scrub is not successful, the resiliency driver to direct future read and write request only to the off-package memory.

11. The method of claim 7 , wherein the off-package memory is a dual in-line memory module in communication with the processor core.

12. The method of claim 7 , wherein the on-package multi-channel dynamic random access memory is an on-chip memory for the central processing unit.

13. A method comprising:

executing a resiliency driver to perform mirroring between an on-package multi-channel dynamic random access memory and an off-package memory;

detecting, by the resiliency driver, a write request including a tag identification;

determining, by the resiliency driver, whether the write request is to be mirrored based on the tag identification; and

in response to a determination that the write request is to be mirrored:

storing, by the resiliency driver, data for the write request to the on-package multi-channel dynamic random access memory as a primary image; and

storing, by the resiliency driver, a backup of the data for the write request to the off-package memory as a secondary image;

detecting, by the resiliency driver, a read request;

reading data for the read request from the on-package multi-channel dynamic random access memory as the primary image;

determining, by the resiliency driver, whether a persistent memory read error has occurred on the on-package multi-channel dynamic random access memory while the data for the read request is being read from the on-package multi-channel dynamic random access memory: and

if the persistent memory read error has occurred, reading the data for the read request from the off-package memory.

14. The method of claim 13 , further comprising:

determining, by the resiliency driver, whether the data read from the off-package memory is correct; and

if the data read from the off-package memory is correct, performing a mirror scrub to write the correct data from the off-package memory to the on-package multi-channel dynamic random access memory.

15. The method of claim 14 , further comprising:

determining, by the resiliency driver, whether the mirror scrub is successful; and

if the mirror scrub is not successful, the resiliency driver to direct future read and write request only to the off-package memory.

16. The method of claim 13 , wherein the off-package memory is a dual in-line memory module in communication with the processor core.

17. The method of claim 13 , wherein the on-package multi-channel dynamic random access memory is an on-chip memory for the central processing unit.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (046366/0014) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060450/0306 →
RELEASE OF SECURITY INTEREST AT REEL 046286 FRAME 0653 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058298/0093 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2019
From: KOLADI, KRISHNAPRASAD; CHALFANT, DAVID K.; BOLLANDOOR, JAGADEESHA; KADABA, SWAMY
To: DELL PRODUCTS, LP
Reel/Frame 048995/0442 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 046286/0653 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 046366/0014 →