IP Library Granted Patent US 10,431,703
Granted Patent B2
US 10,431,703 · App. 15/927,277 · Granted Oct 1, 2019

Optical cladding layer design

Inventors: Erik Johan Norberg (Santa Barbara, CA); Anand Ramaswamy (Pasadena, CA); Brian Robert Koch (Brisbane, CA)
Assignee: Juniper Networks, Inc.
H01L31/0304H01L31/02327H01L31/0328H01L31/109H01S5/02461H01S5/3211H01S5/3213H01S5/021H01S5/026H01S5/1032Y02E10/544
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,431,703
App. No.
15/927,277
Granted
Oct 1, 2019
Kind
B2
Abstract

Embodiments of the invention describe apparatuses, optical systems, and methods related to utilizing optical cladding layers. According to one embodiment, a hybrid optical device includes a silicon semiconductor layer and a III-V semiconductor layer having an overlapping region, wherein a majority of a field of an optical mode in the overlapping region is to be contained in the III-V semiconductor layer. A cladding region between the silicon semiconductor layer and the III-V semiconductor layer has a spatial property to substantially confine the optical mode to the III-V semiconductor layer and enable heat dissipation through the silicon semiconductor layer.

Claims (40)

1. An apparatus, comprising:

a cladding layer defining a longitudinal direction transverse to a first surface of the cladding layer and a lateral direction parallel to the cladding layer, the cladding layer having a first thickness in a first lateral region and a second thickness in a second lateral region, the second thickness being greater than the first thickness;

a silicon semiconductor layer positioned on a second surface of the cladding layer opposite the first surface of the cladding layer; and

a buried oxide layer positioned on the silicon semiconductor layer, wherein the buried oxide layer includes a hole, at least a portion of the hole being longitudinally aligned with at least a portion of the second lateral region.

2. The apparatus of claim 1 , further comprising a thermally conductive material positioned in the hole, the thermally conductive material having a thermal conductivity greater than a thermal conductivity of the buried oxide layer.

3. The apparatus of claim 2 , wherein:

the silicon semiconductor layer has a third thickness in a third lateral region, at least a portion of the third lateral region positioned longitudinally adjacent to at least a portion of the first lateral region;

the buried oxide layer has a fourth thickness in a fourth lateral region, the fourth lateral region being longitudinally adjacent to at least a portion of the third lateral region; and

the thermally conductive material has a fifth thickness in the hole, the fifth thickness being greater than the fourth thickness.

4. The apparatus of claim 3 , further comprising a substrate positioned on the buried oxide layer, the hole extending through the substrate.

5. The apparatus of claim 3 ,

wherein the silicon semiconductor layer has a sixth thickness in a sixth lateral region, the sixth thickness being greater than the third thickness, the sixth lateral region being longitudinally adjacent to at least a portion of the second lateral region;

wherein the hole extends to the silicon semiconductor layer; and

wherein the thermally conductive material in the hole extends to at least the sixth lateral region.

6. The apparatus of claim 5 , wherein a sum of the second and sixth thicknesses equals a sum of the first and third thicknesses.

7. The apparatus of claim 3 ,

wherein the hole extends through the silicon semiconductor layer to the cladding layer; and

wherein the thermally conductive material in the hole extends to at least the second lateral region.

8. The apparatus of claim 3 , further comprising:

a III-V semiconductor layer positioned on the first surface the cladding layer, the III-V semiconductor layer having a seventh thickness in a seventh lateral region, at least a portion of the seventh lateral region positioned longitudinally adjacent to the first lateral region, the III-V semiconductor layer having an eighth thickness in an eighth lateral region, the eighth lateral region positioned longitudinally adjacent to at least a portion of the second lateral region, the eighth thickness being greater than the seventh thickness.

9. The apparatus of claim 8 , wherein the III-V semiconductor layer extends laterally beyond the second lateral region.

10. The apparatus of claim 8 , wherein the first, second, third, sixth, seventh, and eighth lateral regions are shaped to form a waveguide for at least a first wavelength of light.

11. The apparatus of claim 10 , wherein the first, second, third, and sixth lateral regions are shaped to form a thermal shunt of silicon extending into the cladding layer.

12. The apparatus of claim 11 , wherein the thermal shunt has dimensions smaller than the first wavelength of light in the silicon semiconductor layer.

13. The apparatus of claim 10 , wherein the first, second; third, and sixth lateral regions are shaped to form a plurality of thermal shunts of silicon extending into the cladding layer.

14. The apparatus of claim 13 , wherein each thermal shunt has dimensions smaller than the first wavelength of light in the silicon semiconductor layer.

15. The apparatus of claim 1 , wherein the cladding layer includes a dielectric material and has a thermal conductivity less than a thermal conductivity of silicon.

16. An apparatus, comprising:

a cladding layer defining a longitudinal direction transverse to a first surface of the cladding layer and a lateral direction parallel to the cladding layer, the cladding layer having a first lateral region;

a silicon semiconductor layer positioned on a second surface of the cladding layer opposite the first surface of the cladding layer, the silicon semiconductor layer having a third lateral region positioned longitudinally adjacent to the first lateral region, the silicon semiconductor layer having a sixth lateral region positioned longitudinally adjacent to at least a portion of the second lateral region;

a buried oxide layer positioned on the silicon semiconductor layer, the buried oxide layer having a fourth lateral region positioned longitudinally adjacent to at least a portion of the third lateral region, the buried oxide layer including a hole, at least a portion of the hole being longitudinally aligned with at least a portion of the sixth lateral region; and

a thermally conductive material positioned in the hole and extending to at least the sixth lateral region, the thermally conductive material having a thermal conductivity greater than a thermal conductivity of the buried oxide layer.

17. The apparatus of claim 16 , further comprising a substrate positioned on the buried oxide layer, the hole extending through the substrate.

18. The apparatus of claim 16 , wherein the cladding layer has a first thickness in the first lateral region and a second thickness in the second lateral region, the second thickness being greater than the first thickness.

19. An apparatus, comprising:

a cladding layer defining a longitudinal direction transverse to a first surface of the cladding layer and a lateral direction parallel to the cladding layer, the cladding layer having a first lateral region and a second lateral region;

a silicon semiconductor layer positioned on a second surface of the cladding layer opposite the first surface of the cladding layer, the silicon semiconductor layer having a third lateral region positioned longitudinally adjacent to at least a portion of the first lateral region;

a buried oxide layer positioned on the silicon semiconductor layer, the buried oxide layer having a fourth lateral region positioned longitudinally adjacent to at least a portion of the third lateral region, the buried oxide layer and the silicon semiconductor layer defining a hole through the buried oxide layer and the silicon semiconductor layer, at least a portion of the hole being longitudinally aligned with at least a portion of the second lateral region; and

a thermally conductive material positioned in the hole and extending to at least the second lateral region, the thermally conductive material having a thermal conductivity greater than a thermal conductivity of the buried oxide layer.

20. The apparatus of claim 19 , further comprising a substrate positioned on the buried oxide layer, the hole extending through the substrate.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2022
From: AURRION, INC.
To: OPENLIGHT PHOTONICS, INC.
Reel/Frame 061624/0929 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2022
From: JUNIPER NETWORKS, INC.
To: AURRION, INC.
Reel/Frame 059774/0861 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2018
From: NORBERG, ERIK JOHAN; RAMASWAMY, ANAND; KOCH, BRIAN
To: JUNIPER NETWORKS, INC.
Reel/Frame 045300/0616 →
Continuity (3)
Continuation 15361865 · Nov 28, 2016
Continuation 13597701 · Aug 29, 2012
Related Publication 20180219112A1 · Aug 2, 2018