Integrated circuits with memory cell test circuits and methods for producing the same

1. An integrated circuit comprising:

a dummy memory bank area;

a first dummy memory cell positioned within the dummy memory bank area, wherein the first dummy memory cell comprises a fixed layer that is magnetic, a barrier layer that is non-magnetic, and a free layer that is magnetic;

a second dummy memory cell positioned within the dummy memory bank area;

a first dummy top electrode overlying the first dummy memory cell and the second dummy memory cell, wherein the first dummy top electrode is in electrical communication with the first dummy memory cell and the first dummy top electrode is in electrical communication with the second dummy memory cell; and

a test circuit in electrical communication with the first dummy top electrode.

2. The integrated circuit of claim 1 further comprising:

a substrate comprising a substrate surface;

an active memory bank area;

an active memory cell within the active memory bank area; and

an active top electrode overlying the active memory cell, wherein the active top electrode is in electrical communication with the active memory cell, and wherein the active top electrode and the first dummy top electrode are coplanar in an electrode plane that is parallel to the substrate surface.

3. The integrated circuit of claim 2 wherein the active memory cell is electrically isolated from the test circuit.

4. The integrated circuit of claim 2 wherein the dummy memory bank area is adjacent to the active memory bank area such that the dummy memory bank area contacts the active memory bank area.

5. The integrated circuit of claim 4 wherein the dummy memory bank area surrounds the active memory bank area in a plane parallel to the substrate surface.

6. The integrated circuit of claim 2 further comprising:

a scribe area positioned at an outer edge of the integrated circuit, wherein;

the dummy memory bank area is positioned within the scribe area.

7. The integrated circuit of claim 2 wherein:

the first dummy memory cell, the second dummy memory cell, and the active memory cell each comprises the fixed layer that is magnetic, the barrier layer that is non-magnetic, and the free layer that is magnetic.

8. The integrated circuit of claim 2 further comprising:

a second dummy top electrode adjacent to the first dummy top electrode, wherein the second dummy top electrode is electrically isolated from the first dummy top electrode, the second dummy top electrode is in electrical communication with the test circuit, and the second dummy top electrode is coplanar with the first dummy top electrode.

9. The integrated circuit of claim 1 further comprising:

a second dummy top electrode, wherein the second dummy top electrode is adjacent to the first dummy top electrode, and wherein the second dummy top electrode is electrically isolated from the first dummy top electrode.

10. The integrated circuit of claim 9 wherein the second dummy top electrode is in electrical communication with the test circuit.

11. The integrated circuit of claim 1 wherein:

the test circuit comprises a test pad.

12. The integrated circuit of claim 1 further comprising:

a first dummy bottom electrode in electrical communication with the first dummy memory cell;

a second dummy bottom electrode in electrical communication with the second dummy memory cell; and

wherein the first dummy bottom electrode is electrically isolated from the second dummy bottom electrode.

13. An integrated circuit comprising:

a first dummy memory cell;

a test circuit;

a first dummy top electrode overlying the first dummy memory cell, where the first dummy top electrode is in electrical communication with the first dummy memory cell and with the test circuit;

an active memory cell;

an active top electrode overlying the active memory cell, wherein the active top electrode is in electrical communication with the active memory cell and wherein the active top electrode is electrically isolated from the test circuit; and

wherein the active memory cell and the first dummy memory cell comprise a fixed layer that is magnetic, a barrier layer that is non-magnetic, and a free layer that is magnetic.

14. The integrated circuit of claim 13 further comprising:

a substrate comprising a substrate surface;

wherein the active top electrode is coplanar with the first dummy top electrode in an electrode plane that is parallel with the substrate surface.

15. The integrated circuit of claim 14 further comprising:

a scribe area positioned at an outer edge of the integrated circuit, wherein;

the first dummy memory cell is positioned within the scribe area.

16. The integrated circuit of claim 13 further comprising:

a second dummy memory cell in electrical communication with the first dummy top electrode;

a first dummy bottom electrode underlying the first dummy memory cell, wherein the first dummy bottom electrode is in electrical communication with the first dummy memory cell;

a second dummy bottom electrode underlying the second dummy memory cell, wherein the second dummy bottom electrode is in electrical communication with the second dummy memory cell, and wherein;

the first dummy bottom electrode is electrically isolated from the second dummy bottom electrode.

17. The integrated circuit of claim 13 further comprising:

a second dummy top electrode, wherein the second dummy top electrode is adjacent to the first dummy top electrode, and wherein the second dummy top electrode is electrically isolated from the first dummy top electrode.

18. A method of producing an integrated circuit comprising:

forming a first dummy memory cell within a dummy memory bank area, wherein the first dummy memory cell comprises a fixed layer that is magnetic, a barrier layer that is non-magnetic, and a free layer that is magnetic;

forming a second dummy memory cell within the dummy memory bank area;

forming a first dummy top electrode in electrical communication with both the first dummy memory cell and the second dummy memory cell, wherein the first dummy top electrode overlies both the first dummy memory cell and the second dummy memory cell; and

forming a test circuit in electrical communication with the first dummy top electrode.