Differential trace pair system
View Patent ↗A differential trace pair system includes a first conductive layer that is located immediately adjacent a first insulating layer. The system includes a second conductive layer that is located immediately adjacent the first insulating layer and opposite the first insulating layer from the first conductive layer, and includes an aperture that extends through the second conductive layer. A second insulating layer is located immediately adjacent the second conductive layer and opposite the second conductive layer from the first insulating layer. The system includes a first differential trace pair that is included in the second insulating layer and that includes a first differential trace that is positioned adjacent the aperture and references the second conductive layer, and a second differential trace that is longer than the first differential trace and that includes a first portion that is positioned adjacent the second conductive layer aperture and references the first conductive layer.
1. A printed circuit board, comprising:
a first insulating layer;
a first conductive layer that is located immediately adjacent the first insulating layer;
a second conductive layer that is located immediately adjacent the first insulating layer and opposite the first insulating layer from the first conductive layer, wherein the second conductive layer includes a second conductive layer aperture that extends through the second conductive layer;
a second insulating layer that is located immediately adjacent the second conductive layer and opposite the second conductive layer from the first insulating layer, wherein the second conductive layer aperture provides for the engagement of the first insulating layer and the second insulating layer; and
a first differential trace pair that is included in the second insulating layer such that the first differential trace pair is spaced apart from the second conductive layer, wherein first differential trace pair includes:
a first differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer; and
a second differential trace that is longer than the first differential trace and that includes a first portion that is positioned adjacent the second conductive layer aperture and configured to reference to the first conductive layer.
2. The printed circuit board of claim 1 , wherein the referencing of the first portion of the second differential trace is configured to increase a propagation speed of a second differential trace signal transmitted through the first portion of the second differential trace relative to the propagation speed of the second differential trace signal transmitted through a second portion of the second differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer.
3. The printed circuit board of claim 2 , wherein the increase of the propagation speed of the second differential trace signal through the first portion of the second differential trace causes the second differential trace signal to have a predetermined phase mismatch with a first differential trace signal transmitted through the first differential trace.
4. The printed circuit board of claim 1 , wherein the first differential trace includes a serpentine region that includes:
a first portion and a second portion in which the first differential trace and the second differential trace are substantially parallel, and the first differential trace and the second differential trace are spaced apart by a first differential trace pair spacing; and
a third portion that is located between the first portion and the second portion and in which the first differential trace and the second differential trace are substantially parallel, and the first differential trace and the second differential trace are spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.
5. The printed circuit board of claim 1 , further comprising:
a third conductive layer that is located immediately adjacent the second insulating layer and opposite the second insulating layer from the second conductive layer, wherein the third conductive layer includes a third conductive layer aperture that extends through the third conductive layer;
a third insulating layer that is located immediately adjacent the third conductive layer and opposite the third conductive layer from the second insulating layer, wherein the third conductive layer aperture provides for the engagement of the third insulating layer and the second insulating layer; and
a fourth conductive layer that is located immediately adjacent the third insulating layer and opposite the third insulating layer from the third conductive layer, wherein the first portion of the second differential trace is positioned adjacent the third conductive layer aperture and configured to reference to the fourth conductive layer.
6. The printed circuit board of claim 5 , wherein a second portion of the second differential trace is positioned adjacent the third conductive layer aperture and configured to reference to the fourth conductive layer.
7. The printed circuit board of claim 1 , further comprising:
a second differential trace pair that is included in the second insulating layer such that the second differential trace pair is spaced apart from the second conductive layer, wherein the second differential trace pair includes:
a third differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer; and
a fourth differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer, wherein the third differential trace and the first differential trace are spaced apart by a first differential trace pair spacing that prevents a serpentine region from being included in the first differential trace due to a predetermined level of crosstalk.
8. An information handling system (IHS), comprising:
a processor;
a circuit board having a connection pad array that couples the processor to the circuit board, wherein the connection pad array includes a first connection pad, a second connection pad, a third connection pad, and a fourth connection pad, and wherein the circuit board includes:
a first insulating layer;
a first conductive layer that is located immediately adjacent the first insulating layer;
a second conductive layer that is located immediately adjacent the first insulating layer and opposite the first insulating layer from the first conductive layer, wherein the second conductive layer includes a second conductive layer aperture that extends through the second conductive layer;
a second insulating layer that is located immediately adjacent the second conductive layer and opposite the second conductive layer from the first insulating layer, wherein the second conductive layer aperture provides for the engagement of the first insulating layer and the second insulating layer; and
a first differential trace pair that is included in the second insulating layer such that the first differential trace pair is spaced apart from the second conductive layer, wherein first differential trace pair includes:
a first differential trace that extends between the first connection pad and the second connection pad, is positioned adjacent the second conductive layer, and configured to reference to the second conductive layer; and
a second differential trace that extends between the third connection pad and the fourth connection pad, is longer than the first differential trace, and that includes a first portion that is positioned adjacent the second conductive layer aperture and configured to reference to the first conductive layer.
9. The IHS of claim 8 , wherein the referencing of the first portion of the second differential trace is configured to increase a propagation speed of a second differential trace signal transmitted through the first portion of the second differential trace relative to the propagation speed of the second differential trace signal transmitted through a second portion of the second differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer.
10. The IHS of claim 9 , wherein the increase of the propagation speed of the second differential trace signal through the first portion of the second differential trace causes the second differential trace signal to have a predetermined phase mismatch with a first differential trace signal transmitted through the first differential trace.
11. The IHS of claim 8 , wherein the first differential trace includes a serpentine region that includes:
a first portion and a second portion in which the first differential trace and the second differential trace are substantially parallel, and the first differential trace and the second differential trace are spaced apart by a first differential trace pair spacing; and
a third portion that is located between the first portion and the second portion and in which the first differential trace and the second differential trace are substantially parallel, and the first differential trace and the second differential trace are spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.
12. The IHS of claim 8 , further comprising:
a third conductive layer that is located immediately adjacent the second insulating layer and opposite the second insulating layer from the second conductive layer, wherein the third conductive layer includes a third conductive layer aperture that extends through the third conductive layer;
a third insulating layer that is located immediately adjacent the third conductive layer and opposite the third conductive layer from the second insulating layer, wherein the third conductive layer aperture provides for the engagement of the third insulating layer and the second insulating layer; and
a fourth conductive layer that is located immediately adjacent the third insulating layer and opposite the third insulating layer from the third conductive layer, wherein the first portion of the second differential trace is positioned adjacent the third conductive layer aperture and configured to reference to the fourth conductive layer.
13. The IHS of claim 12 , wherein a second portion of the second differential trace is positioned adjacent the third conductive layer aperture and configured to reference to the fourth conductive layer.
14. The IHS of claim 8 , further comprising:
a second differential trace pair that is included in the second insulating layer such that the second differential trace pair is spaced apart from the second conductive layer, wherein the second differential trace pair includes:
a third differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer; and
a fourth differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer, wherein the third differential trace and the first differential trace are spaced apart by a first differential trace pair spacing that prevents a serpentine region from being included in the first differential trace due to a predetermined level of crosstalk.
15. A method for providing a circuit board, comprising:
forming a first conductive layer that is located immediately adjacent a first insulating layer;
forming a second conductive layer that is located immediately adjacent the first insulating layer and opposite the first insulating layer from the first conductive layer, wherein the second conductive layer includes a second conductive layer aperture that extends through the second conductive layer;
forming a second insulating layer that is located immediately adjacent the second conductive layer and opposite the second conductive layer from the first insulating layer, wherein the second conductive layer aperture provides for the engagement of the first insulating layer and the second insulating layer; and
forming a first differential trace pair that is included in the second insulating layer such that the first differential trace pair is spaced apart from the second conductive layer, wherein first differential trace pair includes:
a first differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer; and
a second differential trace that is longer than the first differential trace and that includes a first portion that is positioned adjacent the second conductive layer aperture and configured to reference to the first conductive layer.
16. The method of claim 15 , wherein the referencing of the first portion of the second differential trace is configured to increase a propagation speed of a second differential trace signal transmitted through the first portion of the second differential trace relative to the propagation speed of the second differential trace signal transmitted through a second portion of the second differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer.
17. The method of claim 16 , wherein the increase of the propagation speed of the second differential trace signal through the first portion of the second differential trace causes the second differential trace signal to have a predetermined phase mismatch with a first differential trace signal transmitted through the first differential trace.
18. The method of claim 15 , further comprising:
forming, in the first differential trace, a serpentine region that includes:
a first portion and a second portion in which the first differential trace and the second differential trace are substantially parallel, and the first differential trace and the second differential trace are spaced apart by a first differential trace pair spacing; and
a third portion that is located between the first portion and the second portion and in which the first differential trace and the second differential trace are substantially parallel, and the first differential trace and the second differential trace are spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.
19. The method of claim 15 , further comprising:
forming a third conductive layer that is located immediately adjacent the second insulating layer and opposite the second insulating layer from the second conductive layer, wherein the third conductive layer includes a third conductive layer aperture that extends through the third conductive layer;
forming a third insulating layer that is located immediately adjacent the third conductive layer and opposite the third conductive layer from the second insulating layer, wherein the third conductive layer aperture provides for the engagement of the third insulating layer and the second insulating layer; and
forming a fourth conductive layer that is located immediately adjacent the third insulating layer and opposite the third insulating layer from the third conductive layer, wherein the first portion of the second differential trace is positioned adjacent the third conductive layer aperture and configured to reference to the fourth conductive layer.
20. The method of claim 15 , further comprising:
forming a second differential trace pair that is included in the second insulating layer such that the second differential trace pair is spaced apart from the second conductive layer, wherein the second differential trace pair includes:
a third differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer; and
a fourth differential trace that is positioned adjacent the second conductive layer and configured to reference to the second conductive layer, wherein the third differential trace and the first differential trace are spaced apart by a first differential trace pair spacing that prevents a serpentine region from being included in the first differential trace due to a predetermined level of crosstalk.