Storage array with dynamic cache memory configuration provisioning based on prediction of input-output operations
An apparatus comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive, via a multi-path layer of at least one host device, at least one indication of a predicted distribution of input-output operations directed from the at least one host device to a storage system for a given time interval. The at least one processing device is also configured to determine a cache memory configuration for a cache memory associated with the storage system based at least in part on the at least one indication of the predicted distribution of input-output operations for the given time interval. The at least one processing device is further configured to provision the cache memory with the determined cache memory configuration for the given time interval.
1. An apparatus comprising:
at least one processing device comprising a processor coupled to a memory;
where the at least one processing device is configured:
to receive, via a multi-path layer of at least one host device, at least one indication of a predicted distribution of input-output operations directed from the at least one host device to a storage system for a given time interval;
to determine a cache memory configuration for a cache memory associated with the storage system based at least in part on the at least one indication of the predicted distribution of input-output operations for the given time interval; and
to provision the cache memory with the determined cache memory configuration for the given time interval.
2. The apparatus of claim 1 wherein the multi-path layer comprises at least one multi-path input-output driver configured to control delivery of input-output operations from the at least one host device to particular ports of the storage system over one or more selected ones of a plurality of paths through a network.
3. The apparatus of claim 2 wherein the paths are associated with respective initiator-target pairs with each of a plurality of initiators of the initiator-target pairs comprising a corresponding host bus adaptor of the at least one host device and each of a plurality of targets of the initiator-target pairs comprising a corresponding one of the ports of the storage system.
4. The apparatus of claim 2 wherein the predicted distribution of input-output operations for the given time interval is determined based at least in part on a state of one or more input-output queues of the at least one host device, the state being determined utilizing the at least one multi-path input-output driver.
5. The apparatus of claim 4 wherein the indication of the predicted distribution of input-output operations for the given time interval comprises percentages of different types of input-output commands in the one or more input-output queues of the at least one host device.
6. The apparatus of claim 4 wherein the indication of the predicted distribution of input-output operations for the given time interval comprises at least one of an average input-output size and a peak input-output size determined by performing a time series analysis of historical input-output distributions and the current state of the one or more input-output queues of the at least one host device.
7. The apparatus of claim 2 the at least one indication of the prediction distribution of input-output operations comprises at least one hint delivered via a vendor unique command associated with the at least one multi-path input-output driver.
8. The apparatus of claim 2 wherein receiving the at least one indication of the predicted distribution of input-output operations for the given time interval comprises receiving the at least one indication during the given time interval from the at least one multi-path input-output driver responsive to identifying a burst of input-output activity directed from the at least one host device to the storage system.
9. The apparatus of claim 2 wherein the multi-path layer comprises two or more host devices each associated with at least one multi-path input-output driver configured to control delivery of input-output operations from that host device to particular ports of the storage system over the one or more selected ones of the plurality of paths through the network.
10. The apparatus of claim 9 wherein receiving the at least one indication of the predicted distribution of input-output operations for the given time interval comprises receiving two or more indications of the predicted distribution of input-output operations for the given time interval from the multi-path input-output drivers of the two or more host devices.
11. The apparatus of claim 10 wherein determining the cache memory configuration for the cache memory comprises combining the two or more indications of the predicted distribution of input-output operations for the given time interval received from the multi-path input-output drivers of the two or more host devices.
12. The apparatus of claim 1 wherein the cache memory comprises two or more memory segments, and wherein the determined cache memory configuration comprises a segment size for each of the two or more memory segments.
13. The apparatus of claim 12 wherein a given one of the two or more memory segments comprises two or more pools associated with two or more input-output operation types, and wherein the determined cache memory configuration comprises a fixed cache size for each of the two or more pools.
14. The apparatus of claim 13 wherein the determined cache memory configuration comprises, for the given memory segment, a first fixed cache size for a first one of the two or more pools for a first one of the two or more input-output operation types and a second fixed cache size different than the first fixed cache size for a second one of the two or more pools for a second one of the two or more input-output operation types.
15. A method comprising:
receiving, via a multi-path layer of at least one host device, at least one indication of a predicted distribution of input-output operations directed from the at least one host device to a storage system for a given time interval;
determining a cache memory configuration for a cache memory associated with the storage system based at least in part on the at least one indication of the predicted distribution of input-output operations for the given time interval; and
provisioning the cache memory with the determined cache memory configuration for the given time interval;
wherein the method is performed by at least one processing device comprising a processor coupled to a memory.
16. The method of claim 15 wherein the cache memory comprises two or more memory segments, and wherein the determined cache memory configuration comprises a segment size for each of the two or more memory segments.
17. The method of claim 16 wherein a given one of the two or more memory segments comprises two or more pools associated with two or more input-output operation types, and wherein the determined cache memory configuration comprises a fixed cache size for each of the two or more pools.
18. A computer program product comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code, when executed by at least one processing device comprising a processor coupled to a memory, causes the at least one processing device:
to receive, via a multi-path layer of at least one host device, at least one indication of a predicted distribution of input-output operations directed from the at least one host device to a storage system for a given time interval;
to determine a cache memory configuration for a cache memory associated with the storage system based at least in part on the at least one indication of the predicted distribution of input-output operations for the given time interval; and
to provision the cache memory with the determined cache memory configuration for the given time interval.
19. The computer program product of claim 18 wherein the cache memory comprises two or more memory segments, and wherein the determined cache memory configuration comprises a segment size for each of the two or more memory segments.
20. The computer program product of claim 19 wherein a given one of the two or more memory segments comprises two or more pools associated with two or more input-output operation types, and wherein the determined cache memory configuration comprises a fixed cache size for each of the two or more pools.