Method for fabrication of a CEM device

1. A method for the fabrication of a correlated electron material (CEM) device, the method comprising:

forming a layer of a conductive substrate;

forming a layer of a CEM on the layer of the conductive substrate;

forming a layer of a conductive overlay on the layer of the CEM; and

patterning the layer of the conductive substrate, the layer of the CEM and the layer of the conductive overlay to form a stack comprising the layer of the conductive substrate, the layer of the CEM and the layer of the conductive overlay, wherein the patterning comprises:

forming a hard mask on the layer of the conductive overlay;

dry etching the layer of the conductive overlay and the layer of the CEM to form a partially formed stack, the dry etching of the layer of the CEM to impart damage providing a conductive path between the layer of the conductive overlay and the layer of the conductive substrate at sidewalls of the layer of the CEM;

depositing a coating of a protective polymer over at least sidewalls of the partially formed stack;

dry etching the layer of the conductive substrate;

removing at least a portion of the coating of the protective polymer from the sidewalls of the partially formed stack to expose at least a portion of the sidewalls of the layer of the CEM; and

treating the exposed sidewall portion of the layer of the CEM to remove a portion of the damage to the layer of the CEM at the sidewalls of the layer of the CEM.

2. The method according to claim 1 , comprising: depositing the coating of the protective polymer over a whole of the partially formed stack.

3. The method according to claim 1 , comprising: depositing a fluorocarbon or a hydrofluorocarbon as the coating of the protective polymer.

4. The method according to claim 1 , wherein removing at least a portion of the coating of the protective polymer from the sidewalls further comprises removing at least a portion of the coating of the protective polymer from at least a portion of an upper surface of the layer of the conductive substrate and at least a portion of an upper surface of the hard mask.

5. The method according to claim 1 , wherein treating the exposed sidewall portion of the CEM comprises etching CEM from the sidewalls of the layer of the CEM in the stack to eliminate the portion of the damage at the sidewalls of the layer of the CEM.

6. The method according to claim 5 , wherein the etching of the CEM from the sidewalls of the layer of the CEM in the stack indents the layer of the CEM by 1 nm to 10 nm.

7. The method according to claim 1 , wherein the removing of the at least the portion of the coating of the protective polymer and the treating of the exposed sidewall portion of the layer of the CEM are carried out as a single step.

8. The method according to claim 1 , wherein the layer of the CEM comprises nickel oxide and the completion of the dry etching of the layer of the conductive overlay and the layer of the CEM is determined by monitoring depletion of nickel ion based, at least in part, on attenuation of a nickel-based signal.

9. The method according to claim 1 , wherein depositing the coating of the protective polymer and dry etching of the layer of the conductive substrate are carried out in a single etch chamber.

10. The method according to claim 1 , wherein the layer of the conductive substrate is formed on an insulating substrate including a via contacting the layer of the conductive substrate and a metal interconnect.

11. The method according to claim 1 , further comprising: depositing a cover layer over the stack and patterning the cover layer to form a trench in the cover layer and expose at least a part of the layer of the conductive overlay.

12. The method according to claim 11 , further comprising: depositing a moisture barrier layer over the stack prior to the deposition of the cover layer.

13. The method according to claim 11 , further comprising: depositing a metal barrier layer over the exposed conductive overlay and at least the interior walls of the trench.

14. The method according to claim 13 , further comprising: depositing a metal interconnect over the layer of the conductive overlay and the metal barrier layer to substantially fill the trench.

15. The method according to claim 1 , wherein the layer of the CEM comprises a doped metal compound of a d- or f-block element.

16. A correlated electron material (CEM) device, comprising: a conductive substrate, a CEM layer and a conductive overlay, wherein the CEM layer to have at least one sidewall having, at least in part, a recess as compared to a sidewall of the conductive substrate and a sidewall of the conductive overlay.

17. An integrated circuit comprising: a correlated electron material (CEM) device comprising a conductive substrate, a CEM layer and a conductive overlay, wherein the CEM device to be provided between an upper metal interconnect in a cover layer and a lower metal interconnect in a substrate, the upper metal interconnect and the conductive overlay to have a trench contact, and wherein the CEM layer to have at least one sidewall having, at least in part, a recess therein as compared to a sidewall of the conductive substrate and a sidewall of the conductive overlay.

18. An electronic device comprising: an integrated circuit to have a correlated electron material (CEM) device comprising a conductive substrate, a CEM layer and a conductive overlay, wherein the CEM device to be provided between an upper metal interconnect in a cover layer and a lower metal interconnect in a substrate, the upper metal interconnect and the conductive overlay to have a trench contact, and wherein the CEM layer to have at least one sidewall having, at least in part, a recess as compared to a sidewall of the conductive substrate and a sidewall of the conductive overlay.