Neutron multiplicity detector control circuitry and firmware
Neutron multiplicity detector control logic and firmware may control a neutron multiplicity detector such that higher count rates can be achieved by an order of magnitude of more over conventional control logic and firmware. Count rates of over 1,000,000 cps, and even over 1,500,000 cps, have been realized in some implementations.
1. An apparatus configured to control at least one neutron multiplicity detector, comprising:
at least one processor, comprising:
an ARM processor comprising a direct memory access (DMA) kernel module and a list mode controller (LMC) control user application configured to receive configuration parameters from a user interface (UI); and
programmable logic comprising DMA engine firmware and LMC firmware configured to control the at least one neutron multiplicity detector, wherein
the LMC control user application is configured to write parameter values into the LMC firmware to control aspects of at least one assay providing list mode data.
2. The apparatus of claim 1 , wherein controllable aspects of the at least one assay comprise what channels are active, how long each assay is, whether a veto gate is active, how long digital deadtime is, how many and what size DMA memory buffers are and their location in memory, or any combination thereof.
3. The apparatus of claim 1 , wherein
the DMA kernel module is configured to provide direct memory access to the DMA engine firmware, and
the DMA engine firmware and the DMA kernel module are configured to enable movement of the list mode data directly from the LMC firmware into volatile storage without interaction with the LMC control user application.
4. The apparatus of claim 3 , wherein the DMA kernel module is configured to interrupt the LMC control user application when the list mode data is ready to be written to nonvolatile storage.
5. The apparatus of claim 1 , wherein the at least one neutron multiplicity detector comprises a first neutron multiplicity detector and a second neutron multiplicity detector, and when ready to perform the at least one assay, the LMC firmware is configured to:
send a Pulse Out signal to the first neutron multiplicity detector; and
receive Diff In and transistor-transistor logic (TTL) In signals from the first and second neutron multiplicity detectors, respectively.
6. The apparatus of claim 5 , wherein
Diff In comprises electrical signals emanating from 3 He tubes of the second neutron multiplicity detector, and
TTL In provides electrical signals from 3 He tubes of the first neutron multiplicity detector.
7. The apparatus of claim 5 , wherein
the LMC firmware comprises channel count tracking logic that keeps track of how many neutrons were detected for each data channel, and
each neutron detection generates a respective signal on a line that carries the Pulse Out signal.
8. The apparatus of claim 1 , wherein upon assertion of a Gate In signal, the LMC firmware is configured to cease data collection until the Gate In signal is de-asserted.
9. The apparatus of claim 1 , wherein the LMC firmware comprises:
clock logic that generates a time tag for neutron detections that are recorded in the list mode data and ends each assay when a configured duration has expired;
valid pulse logic that ensures valid pulses are counted that are at least a predetermined number of nanoseconds of nanoseconds of elapsed time, thereby disregarding electrical system noise glitches;
channel control logic that allows a user to turn off a channel; and
channel count tracking logic that keeps track of how many neutrons were detected for each data channel.
10. The apparatus of claim 1 , wherein the programmable logic further comprises:
a plurality of registers storing LMC firmware configuration parameters, health and status information, count rates, and Feynman histograms; and
a first-in, first-out (FIFO) queue.
11. The apparatus of claim 10 , wherein once a neutron detection is deemed valid, the neutron detection is paired with its detection time and transferred into the FIFO queue and provided as part of the list mode data to the DMA firmware engine.
12. The apparatus of claim 1 , wherein
the DMA kernel module configures the DMA engine firmware,
the LMC control user application instructs the DMA kernel module how the DMA engine firmware should be configured, and
the DMA firmware engine informs the DMA kernel module when to interrupt the LMC control user application by sending list mode data to random access memory (RAM), which then sends an interrupt signal to DMA kernel module, which then passes the list mode data to the LMC control user application.
13. The apparatus of claim 1 , wherein the LMC control user application is configured to provide health and status information from registers of the LMC firmware to the UI.
14. At least one processor, comprising:
a direct memory access (DMA) kernel module and a list mode controller (LMC) control user application configured to receive configuration parameters from a user interface (UI), wherein
the LMC control user application is configured to write parameter values into LMC firmware to control aspects of at least one assay providing list mode data.
15. The at least one processor of claim 14 , wherein
the DMA kernel module configures a DMA engine firmware,
the LMC control user application instructs the DMA kernel module how the DMA engine firmware should be configured, and
the DMA firmware engine informs the DMA kernel module when to interrupt the LMC control user application by sending list mode data to random access memory (RAM), which then sends an interrupt signal to DMA kernel module, which then passes the list mode data to the LMC control user application.
16. The at least one processor of claim 14 , wherein controllable aspects of the at least one assay comprise what channels are active, how long each assay is, whether a veto gate is active, how long digital deadtime is, how many and what size DMA memory buffers are and their location in memory, or any combination thereof.
17. At least one processor, comprising:
programmable logic comprising DMA engine firmware and LMC firmware configured to control a first neutron multiplicity detector and a second neutron multiplicity detector, wherein
when ready to perform the at least one assay, the LMC firmware is configured to:
send a Pulse Out signal to the first neutron multiplicity detector; and
receive Diff In and transistor-transistor logic (TTL) In signals from the first and second neutron multiplicity detectors, respectively.
18. The at least one processor of claim 17 , wherein
Diff In comprises electrical signals emanating from 3 He tubes of the second neutron multiplicity detector, and
TTL In provides electrical signals from 3 He tubes of the first neutron multiplicity detector.
19. The at least one processor of claim 17 , wherein the LMC firmware comprises:
clock logic that generates a time tag for neutron detections that are recorded in the list mode data and ends each assay when a configured duration has expired;
valid pulse logic that ensures valid pulses are counted that are at least a predetermined number of nanoseconds of elapsed time, thereby disregarding electrical system noise glitches;
channel control logic that allows a user to turn off a channel; and
channel count tracking logic that keeps track of how many neutrons were detected for each data channel.
20. The at least one processor of claim 17 , wherein
the LMC firmware comprises channel count tracking logic that keeps track of how many neutrons were detected for each data channel, and
each neutron detection generates a respective signal on a line that carries the Pulse Out signal.