IP Library Patent Application 15934416
Patent Application
App. No. 15/934,416

FLASH-DRAM HYBRID MEMORY MODULE

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Quick Facts
Patent No.
US None
App. No.
15/934,416
Abstract

A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.

Claims (6)

1 . A memory module comprising:

a data manager configured to be coupled to a memory controller of a host system using a data bus, the data manager is operable to communicate data signals with the memory controller of the host system by way of the data bus in accordance with a first protocol;

a first volatile memory subsystem coupled to the data manager using a first data bus, the first volatile memory subsystem is operable to communicate data signals with the data manager by way of the first data bus in accordance with the first protocol;

a second volatile memory subsystem coupled to the data manager using a second data bus, the second volatile memory subsystem is operable to communicate data signals with the data manager by way of the second data bus in accordance with the first protocol;

a non-volatile memory subsystem coupled to the data manager using a third data bus, the non-volatile memory subsystem is operable to communicate data signals with the data manager by way of the third data bus using a second protocol; and

a controller operable to receive one or more commands from the memory controller of the host system in accordance with the first protocol, and in response to the one or more commands received from the memory controller of the host system, the controller generates and transmits one or more control signals to the data manager, wherein, in response to the one or more control signals, the data manager transfers data between the first volatile memory subsystem and the memory controller of the host system 1 and transfers data signals from the non-volatile memory subsystem to the second volatile memory subsystem by way of the third data bus and the second data bus.