Semiconductor memory device
A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
1. A semiconductor memory device, comprising:
a memory block including
a first memory string including
a first selection transistor,
a first memory cell, and
a second memory cell, and
a second memory string including
a second selection transistor,
a third memory cell, and
a fourth memory cell;
a first bit line connected to the first memory string and the second memory string;
a first select gate line connected to a gate of the first transistor;
a second select gate line connected to a gate of the second transistor;
a first word line connected to a gate of the first memory cell and a gate of the third memory cell;
a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell; and
a controller configured to
perform an erase operation on the first memory cell, the second memory cell, the third memory cell and the fourth memory cell,
after the erase operation, perform a first verify operation on the first memory cell with a first verify voltage applied to the first word line and on the second memory cell with a second verify voltage applied to the second word line, and
after the first verify operation, perform a second verify operation on the third memory cell with the first verify voltage applied to the first word line not discharged from the first verify operation and on the fourth memory cell with the second verify voltage applied to the second word line not discharged from the first verify operation.
2. The semiconductor memory device of claim 1 , further comprising:
a sense amplifier connected to the first bit line,
wherein the controller is configured to apply an enable signal to the sense amplifier at least twice during the first verify operation and the second verify operations.
3. The semiconductor memory device of claim 2 , wherein
the sense amplifier includes a logic circuit configured to determine whether the first memory string passed or failed the first verify operation and whether the second memory string passed or failed the second verify operation.
4. The semiconductor memory device of claim 3 , wherein
the controller includes a first cache configured to store results of the first verify operation and the second verify operation, and
the sense amplifier includes a second cache configured to store a determination result of the logic circuit.
5. The semiconductor memory device of claim 1 , wherein
the controller is configured to store results of the first verify operation and the second verify operation in a cumulative manner.
6. The semiconductor memory device of claim 5 , wherein
the controller is configured to suspend the first verify operation and the second verify operation when a cumulative number of failures is greater than or equal to a given number.
7. The semiconductor memory device of claim 1 , wherein
each of the first verify operation and the second verify operation includes multiple loops of a sequence of sub verify operations performed for a corresponding one of the first memory string and the second memory string.
8. A method for operating semiconductor memory device,
the semiconductor memory device including:
a memory block including
a first memory string including
a first selection transistor,
a first memory cell, and
a second memory cell, and
a second memory string including
a second selection transistor,
a third memory cell, and
a fourth memory cell;
a first bit line connected to the first memory string and the second memory string;
a first select gate line connected to a gate of the first transistor;
a second select gate line connected to a gate of the second transistor;
a first word line connected to a gate of the first memory cell and a gate of the third memory cell; and
a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell,
the method comprising:
performing an erase operation on the first memory cell, the second memory cell, the third memory cell and the fourth memory cell,
after the erase operation, performing a first verify operation on the first memory cell with a first verify voltage applied to the first word line and on the second memory cell with a second verify voltage applied to the second word line, and
after the first verify operation, performing a second verify operation on the third memory cell with the first verify voltage applied to the first word line not discharged from the first verify operation and on the fourth memory cell with the second verify voltage applied to at the second word line not discharged from the first verify operation.
9. The method of claim 8 , wherein the semiconductor memory device further includes a sense amplifier connected to the first bit line, and an enable signal is applied to the sense amplifier at least twice during the first verify operation and the second verify operations.
10. The method of claim 9 , wherein the sense amplifier includes a logic circuit configured to determine whether the first memory string passed or failed the first verify operation and whether the second memory string passed or failed the second verify operation.
11. The method of claim 10 , wherein the semiconductor memory device further includes a first cache configured to store results of the first verify operation and the second verify operation, and the sense amplifier includes a second cache configured to store a determination result of the logic circuit.
12. The method of claim 8 , further comprising:
storing results of the first verify operation and the second verify operation in a cumulative manner.
13. The method of claim 12 , further comprising:
suspending the first verify operation and the second verify operation when a cumulative number of failures is greater than or equal to a given number.
14. The method of claim 8 , wherein
each of the first verify operation and the second verify operation includes multiple loops of a sequence of sub verify operations performed for a corresponding one of the first memory string and the second memory string.