Three-dimensional semiconductor device
The semiconductor device include a lower insulating layer; a gate stack disposed over the lower insulating layer; a plurality of supports extending from the lower insulating layer toward the gate stack; a source layer disposed between the lower insulating layer and the gate stack; and a channel pattern including a connection part disposed between the source layer and the gate stack.
1. A semiconductor device comprising;
a lower insulating layer;
a gate stack disposed over the lower insulating layer;
a plurality of supports extending from the lower insulating layer toward the gate stack;
a source layer disposed between the lower insulating layer and the gate stack; and
a channel pattern including a connection part disposed between the source layer and the gate stack,
wherein each of the supports overlaps a sidewall of the source layer.
2. The semiconductor device according to claim 1 , wherein the supports support the gate stack and penetrate the source layer.
3. The semiconductor device according to claim 1 , wherein the supports are formed of an insulating material.
4. The, semiconductor device according to claim 1 , further comprising a metal layer disposed between the source layer and the lower insulating layer, wherein the metal layer is penetrated by the supports.
5. The semiconductor device according to claim 1 , further comprising a source contact line extending from the source layer along a sidewall of the gate stack and contacting with the connection part of the channel pattern and the source layer.
6. The semiconductor device according to claim 1 ,
wherein the channel pattern includes pillars extending from the connection part and passing through the gate stack, and
wherein the connection part surrounds the supports.
7. The semiconductor device according to claim 5 , wherein the source contact line comprises a doped semiconductor layer contacting with the source layer and the connection part, and a metal layer formed on the doped semiconductor layer.
8. The semiconductor device according to claim 6 ,
wherein the gate stack comprises gate electrodes and interlayer insulating layers that are alternately stacked, and
wherein the gate electrodes and the interlayer insulating layers surround the pillars.
9. The semiconductor device according to claim 8 , wherein the gate electrodes comprise:
a source select line formed of a stack structure of first conductive material and second conductive material; and
word lines and a drain select line disposed on the source select line and formed of the second conductive material.
10. The semiconductor device according to claim 8 , wherein each of the gate electrodes includes a cell array region and a contact region, and
wherein the gate electrodes are patterned to form a stepped structure in the contact region whereby an end of each gate electrode is exposed through the stepped structure.
11. The semiconductor device according to claim 8 , wherein the pillars are not overlapping the supports.
12. The semiconductor device according to claim 10 , wherein the plurality of pillars are spaced apart in the cell array region a zigzag configuration.
13. The semiconductor device according to claim 12 , wherein the plurality of pillars are divided into a first group and a second group,
wherein each group is controlled by a different drain select line, and
wherein the first and second groups share a common select line and a plurality of common word lines.
14. A semiconductor device comprising:
a lower insulating layer;
a gate stack disposed over the lower insulating layer;
a plurality of supports extending from the lower insulating layer toward the gate stack;
a source layer disposed between the lower insulating layer and the gate stack;
a channel pattern including a connection part disposed between the source layer and the gate stack; and
a source separation insulating layer having a sidewall that is coplanar with an edge of the source layer, and the source separation insulating layer extending onto a sidewall of the connection part.
15. The semiconductor device according to claim 14 , further comprising:
a dummy source layer facing the source layer with the source separation insulating layer interposed therebetween;
peripheral insulating pillars passing through the dummy source layer and extending parallel to the supports;
peripheral contact plugs passing through the respective peripheral insulating pillars and extending into the lower insulating layer; and
driving transistors coupled to the respective peripheral contact plugs.
16. The semiconductor device according to claim 14 , wherein the source separation insulating layer and the supports are formed of the same material.
17. A semiconductor device comprising:
a lower insulating layer;
a gate stack disposed over the lower insulating layer;
a plurality of supports extending from the lower insulating layer toward the gate stack;
a source layer disposed between the lower insulating layer and the gate stack; and
a channel pattern including a connection part disposed between the source layer and the gate stack,
wherein the lower insulating layer includes a first region and a second region, and
wherein the supports extend from the first region of the lower insulating layer.
18. The semiconductor device, according to claim 17 , further comprising a driving transistor disposed below the lower insulating layer to overlap at least one of the first and second regions, and configured to form a peripheral circuit.
19. The semiconductor device according to claim 17 , wherein the plurality of supports are arranged in a zigzag configuration.
20. The semiconductor device according to claim 17 , further comprising a source separation insulating layer having a sidewall that is coplanar with an edge of the source layer, the source separation insulating layer extending onto a sidewall of the connection part, and wherein the source separation insulating layer and the supports are made of a same material.