Ad converter, semiconductor integrated circuit, and rotation detector

1. An AD converter, comprising:

a comparator having an entire input voltage range of from a ground voltage to a power supply voltage;

an analog-to-digital converter (ADC) control circuit;

a correction circuit; and

a storage device,

the comparator including:

a first comparator having an NMOS differential input stage, which is capable of performing normal comparison operation within a range of from a first input voltage, which is higher than the ground voltage and lower than the power supply voltage, to the power supply voltage;

a second comparator having a PMOS differential input stage, which is capable of performing normal comparison operation within a range of from the ground voltage to a second input voltage, which is higher than the first input voltage and lower than the power supply voltage; and

an output selection circuit, which is configured to select any one of an output of the first comparator and an output of the second comparator depending on a magnitude of an input voltage, and

wherein the correction circuit is configured to:

acquire in advance, via the ADC control circuit, a first AD converted value in a case of using the first comparator and a second AD converted value in a case of using the second comparator with respect to a same input voltage in a common region corresponding to a region of an input voltage of the first input voltage or more and the second input voltage or less, in which both the first comparator and the second comparator are capable of performing the normal comparison operation;

calculate a correction value based on the first AD converted value and the second AD converted value, which are obtained with respect to the same input voltage;

store in advance the correction value into the storage device;

perform correction processing based on the correction value to suppress an offset error between the first AD converted value and the second AD converted value; and

output an AD converted value after suppression of the offset error in the entire input voltage range.

2. The AD converter according to claim 1 , wherein the correction circuit is configured to:

calculate in advance a difference between the first AD converted value and the second AD converted value as the correction value; and

perform correction processing of one of addition and subtraction of the correction value, thereby to suppress the offset error between the first AD converted value and the second AD converted value.

3. The AD converter according to claim 1 , wherein the correction circuit is configured to:

hold in advance, as an ideal value, an ideal AD converted value with respect to the same input voltage;

calculate in advance a difference between the first AD converted value and the ideal value as a first correction value;

calculate in advance a difference between the second AD converted value and the ideal value as a second correction value; and

perform correction processing of adding the first correction value to the first AD converted value and correction processing of adding the second correction value to the second AD converted value to suppress the offset error between the first AD converted value and the second AD converted value.

4. An AD converter, comprising:

a comparator having an entire input voltage range of from a ground voltage to a power supply voltage;

an ADC control circuit; and

a correction circuit,

the comparator including:

at least one first comparator having an NMOS differential input stage, which is capable of performing normal comparison operation within a range of from a first input voltage, which is higher than the ground voltage and lower than the power supply voltage, to the power supply voltage; and

at least one second comparator having a PMOS differential input stage, which is capable of performing normal comparison operation within a range of from the ground voltage to a second input voltage, which is higher than the first input voltage and lower than the power supply voltage,

wherein the ADC control circuit is configured to generate a first AD converted value based on an output of the at least one first comparator and a second AD converted value based on an output of the at least one second comparator, and

wherein the correction circuit is configured to:

perform averaging correction processing by using the first AD converted value and the second AD converted value in a common region corresponding to a region of an input voltage of the first input voltage or more and the second input voltage or less, in which both the at least one first comparator and the at least one second comparator are capable of performing the normal comparison operation to suppress an offset error between the first AD converted value and the second AD converted value; and

output an AD converted value after the suppression of the offset error in the entire input voltage range.

5. The AD converter according to claim 4 ,

wherein the correction circuit has an upper limit value and a lower limit value of an AD converted value for defining a range in which the averaging correction processing is performed, the upper limit value and the lower limit value being set in advance, and

wherein the correction circuit is configured to perform weighted averaging processing on the first AD converted value and the second AD converted value as the averaging correction processing with respect to an input voltage for which both the first AD converted value and the second AD converted value are within a range of the lower limit value or more and the upper limit value or less, to thereby suppress the offset error between the first AD converted value and the second AD converted value.

6. The AD converter according to claim 4 ,

wherein the correction circuit has an upper limit value and a lower limit value of an AD converted value for defining a range in which the averaging correction processing is performed, the upper limit value and the lower limit value being set in advance, and

wherein the correction circuit is configured to perform simple averaging processing on the first AD converted value and the second AD converted value as the averaging correction processing with respect to an input voltage for which both the first AD converted value and the second AD converted value are within a range of the lower limit value or more and the upper limit value or less, to thereby suppress the offset error between the first AD converted value and the second AD converted value.

7. An AD converter, comprising:

a plurality of comparators each having an entire input voltage range of from a ground voltage to a power supply voltage;

a majority circuit, which is configured to select one output out of outputs of the plurality of converters;

an output selection circuit; and

an ADC control circuit,

the plurality of comparators including:

a plurality of first comparators having NMOS differential input stages, which are capable of performing normal comparison operation within a range of from a first input voltage, which is higher than the ground voltage and lower than the power supply voltage, to the power supply voltage; and

a plurality of second comparators having PMOS differential input stages, which are capable of performing normal comparison operation within a range of from the ground voltage to a second input voltage, which is higher than the first input voltage and lower than the power supply voltage,

the majority circuit including:

a first majority circuit, which is configured to output a majority result made out of respective outputs from the plurality of first comparators; and

a second majority circuit, which is configured to output a majority result made out of respective outputs from the plurality of second comparators,

wherein the output selection circuit is configured to select and output any one of an output of the first majority circuit and an output of the second majority circuit,

wherein the ADC control circuit is configured to output an AD converted value with respect to the output selected in the output selection circuit, and

wherein an offset error of the AD converted value, which is caused by using any one of the plurality of comparators, is suppressed.

8. The AD converter according to claim 7 ,

wherein the plurality of first comparators include comparators having different transistor sizes, and

wherein the plurality of second comparators include comparators having different transistor sizes.

9. A semiconductor integrated circuit, comprising the AD converter of claim 1 .

10. A semiconductor integrated circuit, comprising the AD converter of claim 4 .

11. A semiconductor integrated circuit, comprising the AD converter of claim 7 .

12. A rotation detector, comprising the semiconductor integrated circuit of claim 9 .

13. A rotation detector, comprising the semiconductor integrated circuit of claim 10 .

14. A rotation detector, comprising the semiconductor integrated circuit of claim 11 .