IP Library Granted Patent US 10,699,980
Granted Patent B2
US 10,699,980 · App. 15/938,741 · Granted Jun 30, 2020

Fan out package with integrated peripheral devices and methods

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Quick Facts
Patent No.
US 10,699,980
App. No.
15/938,741
Granted
Jun 30, 2020
Kind
B2
Abstract

A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

Claims (11)

1. A method, comprising:

coupling a number of die to a batch process carrier in a fan out configuration;

coupling one or more peripheral components adjacent to the number of die on the batch process carrier;

encapsulating the number of die and the one or more peripheral components to form a plurality of encapsulated semiconductor devices; and

thinning the one or more peripheral components while attached to the batch process carrier, wherein thinning the one or more peripheral components includes thinning before the encapsulating step, wherein a resulting thickness of the one or more peripheral components is the same as a thickness of the number of die.

2. The method of claim 1 , further including removing material over each of the one or more peripheral components to expose one or more peripheral component contacts.

3. The method of claim 2 , wherein removing material includes plasma removal.

4. The method of claim 2 , wherein removing material includes laser removal.

5. The method of claim 1 , wherein thinning the one or more peripheral components includes grinding.

6. The method of claim 1 , further including forming a number of integrated routing layers over the number of die and the one or more peripheral components, wherein each integrated routing layer is wider than each die.

7. The method of claim 1 , wherein coupling the number of die to the batch process carrier includes coupling the number of die to a circular wafer carrier.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056337/0609 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2019
From: KESER, LIZABETH; WAIDHAS, BERND; ORT, THOMAS; WAGNER, THOMAS
To: INTEL IP CORPORATION
Reel/Frame 048448/0982 →