Nano-power capacitance-to-digital converter
An asynchronous capacitance-to-digital converter (CDC) is described that allows for very low-power operation when during inactive periods (when no conductive object is in contact or proximity to the sensing electrodes). Asynchronous operation of the CDC provides for capacitance-to-digital conversion without the use of system resources and more power intensive circuit elements.
1. A capacitance-to-digital converter (CDC) comprising:
a comparator having a first input coupled to a first sensing electrode and a second input coupled to a second sensing electrode;
a first capacitive digital-to-analog converter (DAC) coupled to the first input of the comparator, the capacitive DAC for applying a first signal to the first sensing electrode;
a second capacitive digital-to-analog converter (DAC) coupled to the second input of the comparator, the capacitive DAC for applying a second signal to the second sensing electrode; and
a counter for providing control signals to the first and second capacitive DACs, the counter receiving logic signals from a logic unit coupled to an output of the comparator,
wherein a first counter value corresponding to the control signal provided to the first capacitive DAC from a first counter output and a second counter value corresponding to the control signal provided to the second capacitive DAC from a second counter output are in response to a capacitance on at least the first sensing electrode coupled to the first input of the comparator, and
wherein the logic unit comprises:
a first inverter coupled between a first output of the comparator and a first input of an OR gate,
a second inverter coupled between a second output of the comparator and a second input of the OR gate, and
a D flip-flop (F/F) coupled to the first input of the OR gate and the output of the OR gate, the D F/F for providing increment or decrement signals to the counter.
2. The CDC of claim 1 , wherein a first control signal to the first capacitive DAC from the counter is complimentary to a second control signal to the second capacitive DAC from the counter.
3. The CDC of claim 1 , wherein the logic unit determines whether to increment or decrement the counter.
4. The CDC of claim 1 , wherein the first and second capacitive DACs each comprises a coarse capacitive DAC and a fine capacitive DAC coupled to the output of the counter.
5. The CDC of claim 4 , wherein the coarse capacitive DACs comprise a first set of DAC values and the fine capacitive DACs comprises a second set of DAC values, and wherein the first set of DAC values and the second set of DAC values have at least one overlapping value.
6. The CDC of claim 1 further comprising a first zoom capacitor coupled to the first input of the comparator and a second zoom capacitor coupled to the second input of the comparator, the first and second zoom capacitors for applying first and second step signals onto the first and second inputs of the comparator.