Techniques for prefetching data to a first level of memory of a hierarchical arrangement of memory
Examples include techniques to prefetch data from a second level of memory of a hierarchical arrangement of memory to a second level of memory of the hierarchical arrangement of memory. Examples include circuitry for a processor receiving a prefetch request from a core of the processor to prefetch data from the first level to the second level. The prefetch request indicating an amount of data to prefetch that is greater than a data capacity of a cache line utilized by the core.
1. An apparatus comprising:
direct memory access (DMA) circuitry used in connection with a processor, the DMA circuitry to include logic to:
receive a prefetch request from a core of the processor, the prefetch request to prefetch data from a second level of memory included in a hierarchical arrangement of memory coupled with the processor, the data to be prefetched to a first level of memory included in the hierarchical arrangement of memory, the prefetch request to indicate an amount of data to prefetch that is greater than a data capacity of a cache line utilized by the core, the first level of memory to include dynamic random access memory (DRAM) and the second level of memory to include a byte addressable non-volatile memory; and
send one or more access requests to a controller of the second level of memory to cause the data indicated in the prefetch request to be stored to the first level of memory.
2. The apparatus of claim 1 , further comprising the logic to:
send an acknowledgement to the core to indicate receipt of the prefetch request.
3. The apparatus of claim 1 , the hierarchical arrangement of memory comprises two level memory (2LM), the first level of memory coupled with the processor as a near memory and the second level of memory coupled with the processor as a far memory.
4. The apparatus of claim 1 , comprising the amount of data indicated in the prefetch request is at least 1,000 times greater than the data capacity of the cache line utilized by the core.
5. The apparatus of claim 1 , further comprising the DMA circuitry located in an uncore portion of the processor.
6. The apparatus of claim 1 , further comprising the logic to:
detect an overload condition in the hierarchical arrangement of memory that prevents prefetching of at least a portion of the data from the second level of memory to the first level of memory; and
send an indication of the overload condition to the core to cause the core to issue one or more cache line prefetch requests that cause a single cache line of data to be prefetched from the first level of memory for each respective cache line prefetch request in order to prefetch remaining data from the second level of memory to the first level of memory that was not prefetched following the overload condition.
7. The apparatus of claim 1 , further comprising the logic to:
receive an indication from the core that the data to prefetch from the second level of memory is needed for processing by the core before all of the data has been prefetched from the second level of memory; and
stop the sending of the one or more access requests to the controller of the second level of memory.
8. The apparatus of claim 1 , comprising the DRAM maintained on at least one dual in-line memory module (DIMM).
9. The apparatus of claim 1 , comprising the DRAM arranged as high-bandwidth memory (HBM) stacked on the processor.
10. The apparatus of claim 1 , the byte addressable non-volatile memory comprising phase change memory that uses chalcogenide phase change material, flash memory, single or multi-level phase change memory (PCM), nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, resistive memory including a metal oxide base, an oxygen vacancy base and a conductive bridge random access memory (CB-RAM), a spintronic magnetic junction memory, a magnetic tunneling junction (MTJ) memory, a domain wall (DW) and spin orbit transfer (SOT) memory, a thyristor based memory, a magnetoresistive random access memory (MRAM) that incorporates memristor technology, or spin transfer torque MRAM (STT-MRAM).
11. A method comprising:
receiving, at circuitry for a processor, a prefetch request from a core of the processor, the prefetch request to prefetch data from a second level of memory included in a hierarchical arrangement of memory coupled with the processor, the data to be prefetched to a first level of memory included in the hierarchical arrangement of memory, the prefetch request to indicate an amount of data to prefetch that is greater than a data capacity of a cache line utilized by the core, the first level of memory including dynamic random access memory (DRAM) and the second level of memory including a byte addressable non-volatile memory; and
sending one or more access requests to a controller of the second level of memory to cause the data indicated in the prefetch request to be stored to the first level of memory.
12. The method of claim 11 , further comprising:
sending an acknowledgement to the core to indicate receipt of the prefetch request.
13. The method of claim 11 , the hierarchical arrangement of memory comprises two level memory (2LM), the first level of memory coupled with the processor as a near memory and the second level of memory coupled with the processor as a far memory.
14. The method of claim 11 , comprising:
detecting an overload condition in the hierarchical arrangement of memory that prevents prefetching of at least a portion of the data from the second level of memory to the first level of memory; and
sending an indication of the overload condition to the core to cause the core to issue one or more cache line prefetch requests that cause a single cache line of data to be prefetched from the first level of memory for each respective cache line prefetch request in order to prefetch remaining data from the second level of memory to the first level of memory that was not prefetched following the overload condition.
15. The method of claim 11 , comprising:
receiving an indication from the core that the data to prefetch from the second level of memory is needed for processing by the core before all of the data has been prefetched from the second level of memory; and
stopping the sending of the one or more access requests to the controller of the second level of memory.
16. A system comprising:
a hierarchical arrangement of memory that includes a first level of memory and a second level of memory; and
a processor coupled with hierarchical arrangement of memory, the processor to include one or more cores and direct memory access circuitry, the DMA circuitry to include logic to:
receive a prefetch request from a core from among the one or more cores, the prefetch request to prefetch data from the second level of memory, the data to be prefetched to the first level of memory, the prefetch request to indicate an amount of data to prefetch that is greater than a data capacity of a cache line utilized by the core, the first level of memory to include dynamic random access memory (DRAM) and the second level of memory to include a byte addressable non-volatile memory; and
send one or more access requests to a controller of the second level of memory to cause the data indicated in the prefetch request to be stored to the first level of memory.
17. The system of claim 16 , the hierarchical arrangement of memory comprises two level memory (2LM), the first level of memory coupled with the processor as a near memory and the second level of memory coupled with the processor as a far memory.
18. The system of claim 16 , comprising the DMA circuitry located in an uncore portion of the processor.
19. The system of claim 16 , further comprising the logic to:
detect an overload condition in the hierarchical arrangement of memory that prevents prefetching of at least a portion of the data from the second level of memory to the first level of memory; and
send an indication of the overload condition to the core to cause the core to issue one or more cache line prefetch requests that cause a single cache line of data to be prefetched from the first level of memory for each respective cache line prefetch request in order to prefetch remaining data from the second level of memory to the first level of memory that was not prefetched following the overload condition.
20. The system of claim 16 , further comprising the logic to:
receive an indication from the core that the data to prefetch from the second level of memory is needed for processing by the core before all of the data has been prefetched from the second level of memory; and
stop the sending of the one or more access requests to the controller of the second level of memory.
21. The system of claim 16 , comprising the DRAM maintained on at least one dual in-line memory module (DIMM).
22. The system of claim 16 , comprising the DRAM arranged as high-bandwidth memory (HBM) stacked on the processor.