Increasing storage areal density using predictive data locations

1. A method comprising

receiving, by a processor, host data, the host data including first data and extra bit data;

generating, by the processor, run-length limited (RLL) data by encoding the first data with an RLL encoder;

generating, by the processor, a symbol corresponding to at least one bit of the extra bit data; and

generating, by the processor, superpositioned data by inserting the symbol within a contiguous section of repeating bits in the RLL-encoded first data.

2. The method of claim 1 , further comprising identifying, by the processor, a preamble located in the RLL data, the preamble comprising a sequence of repeating bits that is an invalid sequence required by the RLL encoder, the symbol located immediately after the preamble.

3. The method of claim 1 , the generating a symbol corresponding to a bit of the extra bit data comprising modulating, by the processor, the extra bit data using a pre-configured modulation scheme, the pre-configured modulation scheme defining symbol patterns for a one bit and a zero bit.

4. The method of claim 1 , the generating RLL data by encoding the first data with an RLL encoder comprising encoding the first data using an RLL( 3 , 8 ) encoder.

5. The method of claim 1 , further comprising identifying, by the processor, a postamble portion of the RLL-encoded first data, the postamble comprising identifying, by the processor, an invalid contiguous section of repeating bits located after the preamble.

6. The method of claim 5 , the inserting the symbol within a contiguous section of repeating bits in the RLL-encoded first data located immediately after the preamble comprising inserting, by the processor, the symbol between the preamble and the postamble.

7. The method of claim 1 , further comprising:

reading, by the processor, the superpositioned codeword;

identifying, by the processor, the preamble in the superpositioned codeword;

extracting, by the processor, two bits positioned immediately after the preamble; and

demodulating, by the processor, the two bits to retrieve the bit of the extra bit data.

8. The method of claim 1 , further comprising:

performing, by the processor, cyclical redundancy check (CRC) encoding on the host data prior to encoding the first data using a run-length limited (RLL) encoder; and

performing, by the processor, error-code correction (ECC) encoding on the RLL-encoded first data including the symbol.

9. The method of claim 1 , further comprising:

identifying, by the processor, a second symbol corresponding to a second bit of the extra bit data; and

inserting, by the processor, the second symbol in the superpositioned data after the first symbol.

10. The method of claim 9 , further comprising re-encoding, by the processor, the superpositioned data using the RLL encoder prior to inserting the second symbol upon determining that superpositioned data does not include a second contiguous section of repeating bits.

11. A device comprising

a processor; and

a storage medium for tangibly storing thereon program logic for execution by the processor, the stored program logic comprising:

logic, executed by the processor, for receiving host data, the host data including first data and extra bit data;

logic, executed by the processor, for generating run-length limited (RLL) data by encoding the first data with an RLL encoder;

logic, executed by the processor, for generating a symbol corresponding to at least one bit of the extra bit data; and

logic, executed by the processor, for generating superpositioned data by inserting the symbol within a contiguous section of repeating bits in the RLL-encoded first data.

12. The device of claim 11 , the logic further comprising logic, executed by the processor, for identifying a preamble located in the RLL data, the preamble comprising a sequence of repeating bits that is an invalid sequence required by the RLL encoder, the symbol located immediately after the preamble.

13. The device of claim 11 , the logic for generating a symbol corresponding to a bit of the extra bit data comprising logic, executed by the processor, for modulating the extra bit data using a pre-configured modulation scheme, the pre-configured modulation scheme defining symbol patterns for a one bit and a zero bit.

14. The device of claim 11 , the logic for generating RLL data by encoding the first data with an RLL encoder comprising logic, executed by the processor, for encoding the first data using an RLL( 3 , 8 ) encoder.

15. The device of claim 11 , further comprising logic, executed by the processor, for identifying a postamble portion of the RLL-encoded first data, the postamble comprising identifying an invalid contiguous section of repeating bits located after the preamble.

16. The device of claim 14 , the logic for inserting the symbol within a contiguous section of repeating bits in the RLL-encoded first data located immediately after the preamble comprising logic, executed by the processor, for inserting the symbol between the preamble and the postamble.

17. The device of claim 11 , further comprising:

logic, executed by the processor, for reading the superpositioned codeword;

logic, executed by the processor, for identifying the preamble in the superpositioned codeword;

logic, executed by the processor, for extracting two bits positioned immediately after the preamble; and

logic, executed by the processor, for demodulating the two bits to retrieve the bit of the extra bit data.

18. The device of claim 11 , further comprising:

logic, executed by the processor, for performing cyclical redundancy check (CRC) encoding on the host data prior to encoding the first data using a run-length limited (RLL) encoder; and

logic, executed by the processor, for performing error-code correction (ECC) encoding on the RLL-encoded first data including the symbol.

19. The device of claim 11 , further comprising:

logic, executed by the processor, for identifying a second symbol corresponding to a second bit of the extra bit data; and

logic, executed by the processor, for inserting the second symbol in the superpositioned data after the first symbol.

20. The device of claim 19 , further comprising logic, executed by the processor, for re-encoding the superpositioned data using the RLL encoder prior to inserting the second symbol upon determining that superpositioned data does not include a second contiguous section of repeating bits.

21. A system comprising:

a processor;

a persistent storage device; and

a controller configured to access the persistent storage device in response to read and write commands issued by the processor, the controller configured to:

receive host data, the host data including first data and extra bit data;

generate run-length limited (RLL) data by encoding the first data with an RLL encoder;

generate a symbol corresponding to at least one bit of the extra bit data; and

generate superpositioned data by inserting the symbol within a contiguous section of repeating bits in the RLL-encoded first data.

22. The system of claim 21 , the controller further configured to identify a preamble located in the RLL data, the preamble comprising a sequence of repeating bits that is an invalid sequence required by the RLL encoder, the symbol located immediately after the preamble.

23. The system of claim 21 , the persistent storage device comprising a shingled magnetic recording (SMR) device.