Thin-film transistor structures with gas spacer
An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.
1. An integrated circuit comprising:
a first transistor structure;
a second transistor structure, the second transistor structure spaced from the first transistor structure, wherein each of the first transistor structure and the second transistor structure comprises:
a body of semiconductor material with a source region and a drain region;
a gate dielectric layer in contact with the body of semiconductor material; and
a gate electrode in contact with the gate dielectric layer and vertically aligned with the body; and
an insulator material at least partially encapsulating a gas pocket laterally between the first transistor structure and the second transistor structure, wherein the gas pocket is at a same elevation as the gate dielectric layer of each of the first and second transistor structures, and wherein the insulator material is in direct contact with the body of semiconductor material of each of the first and second transistor structures, and wherein the insulator material is in direct contact with the gas pocket.
2. The integrated circuit of claim 1 , wherein the gas pocket is an airgap.
3. The integrated circuit of claim 1 , wherein the gas pocket has a height that is at least 5 nm at it tallest point.
4. The integrated circuit of claim 1 , wherein the gas pocket has a volume of at least 5 nm 3 .
5. The integrated circuit of claim 1 , wherein the gate electrode is on an underlying base, the gate dielectric layer is on the gate electrode, and the body of semiconductor material is on the gate dielectric layer.
6. The integrated circuit of claim 1 , wherein the gas pocket has a vertical size at least as great as a vertical thickness of the body of semiconductor material.
7. The integrated circuit of claim 1 , wherein the gas pocket extends vertically above the body of semiconductor material.
8. The integrated circuit of claim 7 , wherein at least part of the gas pocket is positioned between a first contact on the body of semiconductor material of the first transistor structure and a second contact on the body of semiconductor material of the second transistor structure.
9. The integrated circuit of claim 8 , wherein at least part of the gas pocket is positioned between metal interconnect on the first contact and metal interconnect on the second contact.
10. The integrated circuit of claim 1 , wherein the insulator material completely encapsulates the gas pocket such that the insulator material is on a first sidewall of the first transistor structure and on a second sidewall of the second transistor structure, and wherein at least a portion of the insulator material has a thickness less than 10 nm between the gas pocket and the first sidewall or the second sidewall.
11. The integrated circuit of claim 10 , wherein gas occupies at least 10% of a volume between the first transistor structure and the second transistor structure.
12. The integrated circuit of claim 1 , wherein the first transistor structure and the second transistor structure have a vertical height in a range of 25 nm to 100 nm, and wherein the gas pocket has a height in a range from 5 nm to 90 nm.
13. The integrated circuit of claim 12 , wherein the vertical height of the transistor structure is from 50% to 150% of the height of the gas pocket.