INFORMATION PROCESSING DEVICE, NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM, AND INFORMATION PROCESSING SYSTEM
According to one embodiment, an information processing device includes a nonvolatile memory, assignment unit, and transmission unit. The assignment unit assigns logical address spaces to spaces. Each of the spaces is assigned to at least one write management area included in a nonvolatile memory. The write management area is a unit of an area which manages the number of write. The transmission unit transmits a command for the nonvolatile memory and identification data of a space assigned to a logical address space corresponding to the command.
1 . A memory system comprising:
a nonvolatile memory comprising first and second namespaces; and
a controller configured to control the nonvolatile memory, and communicate with an external processing device, wherein
the first namespace corresponds to a first logical address space of a first program executed in the external processing device, and a second logical address space of a second program executed in the external processing device,
the second namespace corresponds to a third logical address space of a third program executed in the external processing device, and a fourth logical address space of a fourth program executed in the external processing device, and
the controller translates a first logical address in the first or second logical address space to a first physical address indicating a first location in the first namespace, and translates a second logical address in the third or fourth logical address space to a second physical address indicating a second location in the second namespace.
2 . The memory system of claim 1 , wherein
the first logical address space has a first characteristic feature which is different from a second characteristic feature of the second logical address space, and
the third logical address space has a third characteristic feature which is different from a fourth characteristic feature of the fourth logical address space.
3 . The memory system of claim 2 , wherein
the first to fourth characteristic features are first to fourth write frequency features about the first to fourth logical address spaces.
4 . The memory system of claim 1 , wherein
the controller
receives a write command, identification data of a namespace assigned to a logical address space corresponding to the write command, write data, and a third logical address of the write data, from the external processing device,
translates the third logical address to a third physical address of a location in the namespace indicated by the identification data, and
writes the write data to the location in the namespace.
5 . The memory system of claim 1 , wherein
the controller
receives a read command, identification data of a namespace assigned to a logical address space corresponding to the read command, read data, and a logical address of the read data, from the external processing device,
translates the logical address to a physical address of a location in the namespace indicated by the identification data,
reads the read data from the location in the namespace, and
transmits the read data to the external processing device.
6 . The memory system of claim 1 , wherein
the controller comprises a address translation table associating each of the first and second logical addresses with each of the first and second physical addresses, and management data associating each of erase unit areas included in the nonvolatile memory with the first or second namespace.
7 . The memory system of claim 6 , wherein
the nonvolatile memory is a NAND flash memory, and
the erase unit areas are physical blocks.
8 . The memory system of claim 6 , wherein
the controller
receives a configuration command, and
generates the management data based on the configuration command.
9 . The memory system of claim 6 , wherein
the controller
observes a first data storage condition of the first namespace and a second data storage condition of the second namespace, and
allocates each of the erase unit areas to the first or second namespace based on the first and second data storage conditions.
10 . The memory system of claim 9 , wherein
the controller allocates each of the erase unit areas to the first or second namespace such that the first data storage condition is on the same level as the second data storage condition.
11 . The memory system of claim 9 , wherein
the first data storage condition includes a data capacity, an access frequency, a write frequency, the number of accesses, the number of writing, or a data storage ratio about the first namespace, and the second data storage condition includes a data capacity, an access frequency, a write frequency, the number of accesses, the number of writing, or a data storage ratio about the second namespace.
12 . The memory system of claim 1 , wherein
the controller executes garbage collection in each of the first and second namespaces.
13 . The memory system of claim 12 , wherein
the controller changes an empty erase unit area from the first namespace to the second namespace after the garbage collection in the first namespace, to execute wear leveling between the first namespace and the second namespace.
14 . The memory system of claim 12 , wherein
the nonvolatile memory comprises each of first and second provisioning areas corresponding to each of the first and second namespaces.
15 . The memory system of claim 12 , wherein
the controller comprises first and second buffer memories corresponding to the first and second namespaces.
16 . A memory system comprising:
a nonvolatile memory comprises first and second namespaces; and
a controller configured to control the nonvolatile memory, and communicate with a processing device, wherein
the first namespace corresponds to a first logical address space of a first program executed in the processing device, and a second logical address space of a second program executed in the processing device,
the second namespace corresponds to a third logical address space of a third program executed in the processing device, and
the controller translates a first logical address in the first or second logical address space to a first physical address indicating a first location in the first namespace, and translates a second logical address in the third logical address space to a second physical address indicating a second location in the second namespace.