Charge trapping split gate device and method of fabricating same

1. A split gate device, comprising:

a select gate disposed over a substrate;

a memory gate disposed over the substrate;

a dielectric structure having a first portion disposed between the memory gate and the substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate;

first and second silicide layers disposed over the select gate and the memory gate respectively; and

a spacer formed over the select gate along an inner sidewall of the memory gate, the spacer covering a portion of the inner sidewall of the memory gate that extends above a top surface of the select gate, wherein the spacer is disposed directly above a top surface of the second portion of the dielectric structure, and wherein the spacer is disposed above the top surface of the select gate partially such that at least a portion of the top surface of the select gate is not covered by the spacer.

2. The split gate device of claim 1 , wherein a height of the memory gate is greater than a height of the select gate.

3. The split gate device of claim 1 , wherein a top surface of the memory gate has a greater elevation than the top surface of the select gate.

4. The split gate device of claim 1 , wherein the dielectric structure further comprises an oxide-nitride-oxide configuration.

5. The split gate device of claim 1 , wherein the spacer insulates the first silicide layer from the memory gate.

6. The split gate device of claim 1 , further comprising an outer spacer disposed respectively adjacent to an outer sidewall of the select gate and memory gate.

7. A device, including:

a substrate divided into a core region and a periphery region,

wherein the core region comprises at least one memory device formed on the substrate, each memory device including,

a select gate disposed adjacent to a memory gate over the substrate,

a dielectric structure having a first portion disposed underneath the memory gate and a second portion disposed between and separating the select gate from the memory gate,

a spacer formed over the select gate, insulating the memory gate and select gate from one another, wherein the spacer is disposed directly above a top surface of the second portion of the dielectric structure, and wherein the spacer is disposed above the top surface of the select gate partially such that at least a portion of the top surface of the select gate is not covered by the spacer, and

wherein the periphery region comprises at least one first type of transistor and at least one second type of transistor formed on the substrate, wherein a first gate dielectric of the at least one first type of transistor is thicker than a second gate dielectric of the at least one second type of transistor.

8. The device of claim 7 , wherein the at least one first type of transistor is a high voltage (HV) transistor and the at least one second type of transistor is a low voltage (LV) transistor.

9. The device of claim 8 , wherein the HV transistor comprises a HV gate and the LV transistor comprises a LV gate, and wherein a top surface of the HV gate has an approximately same elevation of a top surface of the LV gate.

10. The device of claim 9 , wherein the top surfaces of the HV and LV gates have the approximately same elevation of a top surface of the select gate.

11. The device of claim 7 , wherein a top surface of the memory gate has a greater elevation than a top surface of the select gate.

12. The device of claim 7 , wherein the spacer is formed covering a portion of an inner sidewall of the memory gate that extends above a top surface of the select gate.

13. The device of claim 7 , wherein the dielectric structure comprises a charge-trapping nitride layer disposed between two oxide layers.

14. The device of claim 7 , wherein the dielectric structure has an L-shape, the first portion being substantially vertical, and the second portion being substantially horizontal, and wherein the first and second portions are formed integrally.

15. The device of claim 7 , wherein each of the memory devices further comprises:

first and second silicide layers disposed overlying the select gate and the memory gate respectively.

16. A system-on-chip (SOC) device, comprising:

a memory array including a plurality of memory cells, wherein each memory cell includes,

a select gate disposed adjacent to a memory gate and over a substrate, wherein a top surface of the memory gate has a greater elevation than a top surface of the select gate,

a dielectric structure having a first portion disposed underneath the memory gate and a second portion disposed between and separating the select gate from the memory gate,

a spacer formed over the select gate, insulating the memory gate and select gate from one another, wherein the spacer is disposed directly above a top surface of the second portion of the dielectric structure, and wherein the spacer is disposed above the top surface of the select gate partially such that at least a portion of the top surface of the select gate is not covered by the spacer; and

a peripheral circuitry comprising,

a plurality of first transistors, each first transistor including a first gate dielectric disposed underneath a first gate, and

a plurality of second transistors, each second transistor including a second gate dielectric disposed underneath a second gate,

wherein the first gate dielectric has a greater thickness than the second gate dielectric, and wherein top surfaces of the first and second gates have an approximately same elevation.

17. The SOC device of claim 16 , wherein the memory array and the peripheral circuitry are embedded in a single substrate.

18. The SOC device of claim 16 , wherein the memory cell further comprises first and second silicide layers disposed over the select gate and the memory gate respectively.

19. The SOC device of claim 16 , wherein the select gate of the memory cell, the first gate of the first transistor, and the second gate of the second transistor are formed concurrently with a same material such that top surfaces of the select, first, and second gates have the approximately same elevation.

20. The split gate device of claim 1 , wherein the spacer is formed over a portion of the first silicide layer.