System on a chip with multiple cores
An apparatus includes multiple radio-frequency (RF) circuits, a number of Bluetooth (BT) cores and a processor. The BT cores are coupled to the plurality of RF circuits. The processor is coupled to the BT cores to control operations of the RF circuits and the BT cores. The RF circuits, the BT cores and the processor are implemented as a system on a chip (SoC). Controlling the operations of the RF circuits and the BT cores can be performed by controlling register spaces associated with the RF circuits and the BT cores.
1. An apparatus comprising:
a plurality of radio-frequency (RF) circuits;
a plurality of Bluetooth (BT) cores coupled to the plurality of RF circuits; and
a processor coupled to the plurality of BT cores and configured to control operations of the plurality of RF circuits and the plurality of BT cores,
wherein:
the plurality of RF circuits and the plurality of BT cores are implemented on a system on a chip (SOC) and are configured to simultaneously maintain multiple active links,
the plurality of RF circuits and the plurality of BT cores include register spaces, and
controlling the operations of the plurality of RF circuits and the plurality of BT cores are performed by controlling the register spaces included in the plurality of RF circuits and the plurality of BT cores.
2. The apparatus of claim 1 , wherein each of the plurality of BT cores is implemented as a media access control (MAC) unit and a modem, wherein modems of the plurality of BT cores are configured to communicate to one another.
3. The apparatus of claim 2 , further comprising a common modem interface configured to couple the modems of the plurality of BT cores to at least some of MAC units.
4. The apparatus of claim 3 , wherein the common modem interface is configured to couple the modems of the plurality of BT cores to the processor.
5. The apparatus of claim 1 , wherein each of the plurality of BT cores is configured to simultaneously receive signals from one or more transmitting devices via one or more receive paths having similar or different channel frequencies.
6. The apparatus of claim 1 , wherein the plurality of BT cores are configured to simultaneously transmit signals to one or more receiving devices.
7. The apparatus of claim 6 , wherein the processor is configured to perform a frequency management and an antenna desensing scheme for the plurality of BT cores to simultaneously transmit signals to two or more receiving devices.
8. The apparatus of claim 1 , wherein the plurality of BT cores are configured to handle multiple connections, and wherein the processor is configured to perform a frequency management to prevent a single channel frequency to be simultaneously used by more than one connection.
9. The apparatus of claim 1 , wherein the plurality of BT cores are configured to handle multiple connections, and wherein the processor is configured to perform a timing management to prevent overlapping of a receive (RX) time of a BT core with a transmit (TX) time of another BT core of the plurality of BT cores.
10. The apparatus of claim 1 , wherein the processor is configured to combine, using a maximum-ratio combining (MRC) process, signals received from a single source by two or more BT cores of the plurality of BT cores to increase an Rx sensitivity of the apparatus.
11. The apparatus of claim 10 , wherein the processor is configured identify an RF circuit of the plurality of RF circuits and a channel frequency that are suitable for transmission to a receiving device and to use the RF circuit and the channel frequency, in a Tx beamforming process, to transmit to the receiving device, wherein the identification is based on information obtained during the MRC process.
12. A method of implementing multiple Bluetooth (BT) cores system on a chip (SoC), the method comprising:
implementing a plurality of radio-frequency (RF) circuits on a chip;
coupling a plurality of Bluetooth (BT) cores implemented on the chip to the plurality of RF circuits;
coupling a processor implemented on the chip to the plurality of BT cores via a bus; and
configuring the processor to control operations of the plurality of RF circuits and the plurality of BT cores,
wherein:
the plurality of RF circuits and the plurality of BT cores are implemented on a SOC and are configured to simultaneously maintain multiple active links,
the plurality of RF circuits and the plurality of BT cores include register spaces, and
controlling, by the processor, the operations of the plurality of RF circuits and the plurality of BT cores comprises controlling the register spaces included in plurality of RF circuits and the plurality of BT cores.
13. The method of claim 12 , further comprising implementing each of the plurality of BT cores as a media access control (MAC) unit and a modem and configuring modems of the plurality of BT cores to communicate to one another.
14. The method of claim 13 , further comprising implementing on the chip a common modem interface to couple the modems of the plurality of BT cores to at least some of MAC units and to couple the modems of the plurality of BT cores to the processor.
15. The method of claim 12 , further comprising configuring the processor to perform a frequency management and an antenna desensing scheme for the plurality of BT cores to simultaneously transmit signals to two or more receiving devices.
16. The method of claim 12 , further comprising configuring the processor to combine, using a maximum-ratio combining (MRC) process, signals received from a single source by two or more BT cores of the plurality of BT cores to increase an Rx sensitivity of the multiple BT cores SoC.
17. The method of claim 16 , further comprising configuring the processor to identify an RF circuit of the plurality of RF circuits and a channel frequency that are suitable for transmission to a receiving device and to use the RF circuit and the channel frequency and to perform a Tx beamforming process to transmit to the receiving device, wherein the identification is based on information obtained during the MRC process.
18. The method of claim 16 , wherein configuring the processor to perform the MRC process comprises configuring the processor to control:
two or more of the plurality of RF circuits to receive signals from the single source and to pass the received signal to respective modems;
the respective modem to pass respective modem signals to a single modem;
the single modem to suitably combine the respective modem signals and to provide a combined modem signal to a single MAC unit; and
the single MAC unit to provide a respective MAC signal to the processor.
19. A wireless communication device comprising:
a radio-frequency (RF) block including a plurality of Bluetooth (BT) RF circuits;
a baseband circuit including a plurality of BT cores coupled to the plurality of BT RF circuits; and
a processor coupled to the plurality of BT cores and configured to control operations of the plurality of BT RF circuits and the plurality of BT cores,
wherein:
the plurality of BT RF circuits and the plurality of BT cores include register spaces,
at least the plurality of BT RF circuits, the plurality of BT cores and the processor are implemented as system on a chip (SoC), and the plurality of BT RF circuits and the plurality of BT cores are configured to simultaneously maintain multiple active links, and
the processor is configured to control the operations of the plurality of BT RF circuits and the plurality of BT cores by controlling the register spaces included in the plurality of BT RF circuits and the plurality of BT cores.
20. The wireless communication device of claim 19 , wherein each of the plurality of BT cores is implemented as a media access control (MAC) unit and a modem, wherein modems of the plurality of BT cores are configured to communicate to one another, and wherein the baseband circuit further comprises a common modem interface configured to couple the modems of the plurality of BT cores to at least some of MAC units and to couple the modems of the plurality of BT cores to the processor.