Decision feedback equalizer for single-ended signals to reduce inter-symbol interference
View Patent ↗The present invention is directed to communication systems and methods thereof. More specifically, an embodiment of the present invention includes a buffer that is coupled to a reference terminal. A shift register stores decision levels for post-cursor positions. A plurality of switches converts the decision levels to equalization currents during an equalization process. The equalization currents are converted to equalization voltage terms by one or more load resistors. The buffer is provided between the reference terminal and the one or more load resistors. There are other embodiments as well.
1. A decision feedback equalization (DFE) system comprising:
an input terminal for receiving an input voltage;
a reference terminal for receiving a reference voltage;
a buffer module connected to the reference terminal via a buffer input;
a first drop resistor coupled to the buffer module via a buffer output;
a second drop resistor coupled to buffer output and the first drop resistor;
a shift register comprising n flip-flops for storing equalization decision levels; and
a switching module comprising n switches electrically coupled to the n flip-flops, the n switches including a first switch, the first switch comprising a pair of current sources and a pair of matching NMOS transistors, the first drop resistor being directly coupled to a first NMOS transistor of the matching NMOS transistors, the second drop resistor being directly coupled to a second NMOS transistor of the matching NMOS transistors, wherein the switching module is configured to provide equalization voltage by generating equalization current using decision levels stored at the shift register to the first drop resistor.
2. The system of claim 1 wherein:
the first switch further comprises a pair of matching PMOS transistors, the matching PMOS transistors comprising a first PMOS transistor and a second PMOS transistor, the first drop resistor being directly coupled to the first PMOS transistor of the matching PMOS transistors, the second drop resistor being directly coupled to the second PMOS transistor of the matching PMOS transistors;
the pair of current sources is matched.
3. The system of claim 1 wherein the equalization decision levels are associated with inter-symbol interference.
4. The system of claim 1 wherein the n flip-flops stores n decision levels corresponding to n post-cursor positions.
5. The system of claim 1 wherein the shift register comprising a sampler for sampling interference decision levels.
6. A decision feedback equalization (DFE) system comprising:
an input terminal for receiving an input voltage;
a reference terminal for receiving a reference voltage;
a feedback module comprising a feedback input and a first feedback output and a second feedback output, the feedback input being coupled to the reference terminal;
a buffer module connected to the reference terminal via the feedback module;
a first drop resistor coupled to the buffer module via a buffer output of the buffer module;
a second drop resistor coupled to the buffer module via the buffer output;
a shift register comprising n flip-flops for storing equalization decision levels, the shift register being coupled to the first drop resistor; and
a switching module comprising n switches electrically coupled to the n flip-flops, the n switches including a first switch, the first switch comprising a first current source and a first pair of MOS devices, the first pair of MOS devices comprising a first MOS device and a second MOS device, the first MOS device being coupled to the first drop resistor, the second MOS device being coupled to the second drop resistor, wherein the switching module is configured to provide equalization voltage by generating equalization current using decision levels stored at the shift register to the first drop resistor.
7. The device of claim 6 wherein the feedback module is configured to operate in a common mode and to stabilize the reference voltage.
8. The device of claim 6 wherein the first switch comprises a pair of differential NMOS transistors.
9. The device of claim 6 wherein the reference terminal is coupled to a DC path.
10. The device of claim 6 wherein the input voltage is received from a memory bus.
11. A decision feedback equalization (DFE) system comprising:
an input terminal for receiving an input voltage;
a reference terminal for receiving a reference voltage;
a buffer module connected to the reference terminal via a buffer input, the buffer module being substantially isolated from the input terminal;
a first drop resistor coupled to the buffer module via a buffer output;
a second drop resistor coupled to buffer output and the first drop resistor;
a shift register comprising n flip-flops for storing equalization decision levels; and
a switching module comprising n switches electrically coupled to the n flip-flops, the n switches including a first switch, the first switch comprising a pair of current sources and a pair of matching NMOS transistors, the first drop resistor being directly coupled to a first NMOS transistor of the matching NMOS transistors, the second drop resistor being directly coupled to a second NMOS transistor of the matching NMOS transistors, wherein the switching module is configured to provide equalization voltage by generating equalization current using decision levels stored at the shift register to the first drop resistor.
12. The system of claim 11 wherein the reference voltage is substantially independent from the input voltage.
13. The system of claim 12 wherein the decision levels are associated with post-cursor positions of a previous signal.
14. The system of claim 11 wherein each of the n flip-flop corresponds to a decision feedback equalization tap.
15. The system of claim 11 wherein the pair of current sources are matched.
16. The system of claim 11 wherein the buffer module comprises one or more chopping amplifiers.
17. The system of claim 11 wherein the reference voltage is coupled to a DC path.
18. The system of claim 11 wherein the pair of current sources are turned on when the equalization voltage is needed.
19. The system of claim 11 wherein the first switch comprises a pair of differential NMOS resistors and a pair of differential PMOS resistors.
20. The system of claim 11 further comprising the second drop resistor configured in parallel to the first drop resistor.