Mass storage device with host initiated buffer flushing
An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer memory is to store less bits per cell than the non volatile primary storage memory. The solid state drive includes a controller to flush the buffer in response to a buffer flush command received from a host. The controller is to cause the solid state drive to service read/write requests that are newly received from the host in between flushes of smaller portions of the buffer's content that are performed to service the buffer flush command.
1. An apparatus, comprising:
a solid state drive comprising non volatile buffer memory and non volatile primary storage memory, said non volatile buffer memory to store less bits per cell than said non volatile primary storage memory, said solid state drive comprising a controller to flush said non volatile buffer memory in response to a buffer flush command received from a host, said controller to cause said solid state drive to service read/write requests that are newly received from said host in between flushes of smaller portions of content of said non volatile buffer memory, said flushes of said smaller portions of said content of said non volatile buffer memory being performed to service said buffer flush command so that said controller interleaves said flushes of said smaller portions of said content of said non volatile buffer memory with respective nominal services of said read/write requests thereby creating an idle time in said solid state drive in which said solid state drive is not servicing said read/write requests or performing said flushes of said smaller portions of said content of said non volatile buffer memory so that said solid state drive is able to enter a low power state within said idle time.
2. The apparatus of claim 1 wherein said non volatile buffer memory and said non volatile primary storage memory are composed of flash storage cells.
3. The apparatus of claim 2 wherein said non volatile buffer memory is composed of single level cell (SLC) flash storage cells.
4. The apparatus of claim 3 wherein said non volatile primary storage memory is composed of quad level cell (QLC) storage cells.
5. The apparatus of claim 1 wherein said non volatile buffer memory is composed of a static buffer memory and a dynamic buffer memory.
6. The apparatus of claim 5 wherein said static buffer memory and said dynamic buffer memory are both composed of SLC flash storage cells.
7. The apparatus of claim 1 wherein said solid state drive comprises a NVM express (NVMe) interface through which said buffer flush command is received from said host.
8. The apparatus of claim 1 wherein said controller is to cause said solid state drive to cease further flushing of said non volatile buffer memory in response to a cancel flush command received from said host.
9. The apparatus of claim 1 wherein said controller is to update a log to indicate completion of said buffer flush command.
10. The apparatus of claim 1 wherein said smaller portions are determined as a number of pages equal to a multiple of a number of bits that are stored per storage cell of said non volatile primary storage memory.
11. An apparatus, comprising:
a semiconductor chip comprising host side logic circuitry to send a stream of read/write requests to a solid state drive and to insert a buffer flush command to said solid state drive within said stream of read/write requests, wherein, in response to said buffer flush command being inserted within said stream of read/write requests, said solid state drive will interleave servicing of nominal read/write activity of the solid state drive with flushes of smaller portions of a non volatile buffer memory to a non volatile primary storage memory, wherein, the interleaving of the servicing of the nominal read/write activity of the solid state drive with the flushing of the smaller portions of the non volatile buffer memory to the non volatile primary storage memory is to create an idle time in the solid state drive in which the solid state drive is not servicing read/write requests from the host or performing flushes so that the solid state drive is able to enter a low power state.
12. The apparatus of claim 11 wherein said host side logic circuitry is part of a peripheral control hub.
13. The apparatus of claim 12 wherein said peripheral control is to communicate to said solid state drive through an NVM express (NVMe) interface.
14. A computing system, comprising:
a plurality of processing cores;
a main memory;
a main memory controller coupled between said main memory and said plurality of processing cores; and,
a peripheral control hub coupled to a solid state drive, solid state drive comprising non volatile buffer memory and non volatile primary storage memory, said non volatile buffer memory to store less bits per cell than said non volatile primary storage memory, said solid state drive comprising a controller to flush said non volatile buffer memory in response to a buffer flush command received from a host, said controller to cause said solid state drive to service read/write requests that are newly received from said host in between flushes of smaller portions of content of said non volatile buffer memory, said flushes of said smaller portions of said content of said non volatile buffer memory being performed to service said buffer flush command so that said controller interleaves said flushes of said smaller portions of said content of said non volatile buffer memory with respective nominal services of said read/write requests thereby creating an idle time in said solid state drive in which said solid state drive is not servicing said read/write requests or performing said flushes of said smaller portions of said content of said non volatile buffer memory so that said solid state drive is able to enter a low power state within said idle time.
15. The computing system of claim 14 wherein said solid state drive comprises an NVM express (NVMe) interface through which said buffer flush command is received from said host.
16. The computing system of claim 14 wherein said controller is to cause said solid state drive to cease further flushing of said buffer in response to a cancel flush command received from said host.
17. The computing system of claim 14 wherein said controller is to update a log to indicate completion of said buffer flush command.
18. The computing system of claim 14 wherein said smaller portions are determined as a number of pages equal to a multiple of a number of bits that are stored per storage cell of said non volatile primary storage memory.
19. The computing system of claim 14 wherein said non volatile buffer memory is composed of single level cell (SLC) flash cells and said non volatile primary storage memory is composed of flash cells that store more than one bit per cell.
20. A method performed by a solid state drive, comprising:
receiving a buffer flush command from a host;
receiving read/write requests from said host; and,
flushing smaller portions of content from a buffer of said solid state drive in between respective services of said read/write requests such that said flushing of said smaller portions is interleaved with said services of said read/write requests, said interleaving of said smaller portions with said services of said read/write requests to create an idle time in the solid state drive in which said solid state drive is not performing reads, not performing writes and not performing flushes from said buffer so that said solid state drive is able to enter a low power state within said idle time.