IP Library Granted Patent US 10,599,572
Granted Patent B2
US 10,599,572 · App. 15/953,770 · Granted Mar 24, 2020

Method and device for optimization of data caching

Inventors: Wei Cui (Shanghai, CN); Denny Dengyu Wang (Shanghai, CN); Jian Gao (Beijing, CN); Lester Zhang (Beijing, CN); Chen Gong (Beijing, CN)
Assignee: EMC IP Holding Company LLC
G06F12/0864G06F3/0604G06F3/065G06F3/0641G06F3/0679G06F12/082G06F12/0895G06F2212/1024G06F2212/608
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Quick Facts
Patent No.
US 10,599,572
App. No.
15/953,770
Granted
Mar 24, 2020
Kind
B2
Abstract

The embodiments of the present disclosure provide a computer-implemented method. The method includes caching data from a persistent storage device into a cache. The method also includes caching a physical address and a logical address of the data in the persistent storage device into the cache. The method further includes in response to receiving an access request for the data, accessing the data cached in the cache using at least one of the physical address and the logical address. The embodiments of the present disclosure also provide an electronic apparatus and a computer program product.

Claims (79)

1. A computer-implemented method, comprising:

caching data from a persistent storage device into a cache;

caching a physical address and a logical address of the data in the persistent storage device into the cache;

caching an indicator into the cache;

setting the indicator to a positive state or a negative state to indicate whether the data is directly rewritable in the cache; and

in response to receiving an access request for the data, accessing the data cached in the cache using at least one of the physical address and the logical address, wherein accessing the data cached in the cache comprises:

in response to the access request being a rewrite request, determining whether the indicator is in the positive state or in the negative state;

in response to determining that the indicator is in the positive state, directly performing a rewrite operation on the data in the cache; and

in response to determining that the indicator is in the negative state,

caching data for rewriting in a further position in the cache, and

setting an indicator indicating whether the data for rewriting is directly rewritable to the positive state.

2. The method of claim 1 , wherein caching the physical address and the logical address into the cache comprises:

caching the physical address and the logical address using a two-dimensional hash table.

3. The method of claim 2 , wherein the two-dimensional hash table includes:

a first dimensional hash table for mapping the physical address to the logical address and the data by using the physical address as a key, and

a second dimensional hash table for mapping the logical address to the physical address by using the logical address as a key.

4. The method of claim 1 , wherein:

the logical address corresponds to one physical address or is prevented from corresponding to any physical addresses; and

the physical address corresponds to at least one of a plurality of logical addresses or is prevented from corresponding to any logical addresses.

5. The method of claim 1 , wherein setting the indicator comprises:

if the physical address corresponds to the logical address only, setting the indicator to the positive state; and

if the physical address corresponds to a plurality of logical addresses, or it is undetermined whether the physical address corresponds to the logical address only, setting the indicator to the negative state.

6. The method of claim 1 , wherein setting the indicator further comprises:

in response to performing at least one of a snapshot operation and a deduplication operation on the data in the storage device, setting the indicator to the negative state.

7. The method of claim 1 , wherein caching the data from the storage device into the cache comprises:

in response to a request for a read operation on the data, determining whether the data is cached in the cache;

in response to determining that the data is absent from the cache,

duplicating the data from the storage device into the cache; and

setting the indicator to the negative state.

8. The method of claim 1 , wherein the persistent storage device and the cache belong to a storage system which performs data storage operations on behalf of a set of external client computers; and

wherein caching the data from the persistent storage device into the cache includes:

accessing, as the data from the persistent storage device, snapshotted client data provided by the set of external client computers.

9. The method of claim 1 , wherein the persistent storage device and the cache belong to a storage system which performs data storage operations on behalf of a set of external client computers; and

wherein caching the data from the persistent storage device into the cache includes:

accessing, as the data from the persistent storage device, deduplicated client data provided by the set of external client computers.

10. An electronic apparatus, comprising:

at least one processor; and

at least one memory including computer instructions, the at least one memory and the computer instructions being configured, with the processor, to cause the electronic apparatus to:

cache data from a persistent storage device into a cache;

cache a physical address and a logical address of the data in the persistent storage device into the cache;

cache an indicator into the cache;

set the indicator to a positive state or a negative state to indicate whether the data is directly rewritable in the cache;

in response to receiving an access request for the data, access the data cached in the cache using at least one of the physical address and the logical address;

in response to the access request being a rewrite request, determine whether the indicator is in the positive state or in the negative state;

in response to determining that the indicator is in the positive state, directly perform a rewrite operation on the data in the cache; and

in response to determining that the indicator is in the negative state,

cache data for rewriting in a further position in the cache; and

set an indicator indicating whether the data for rewriting is directly rewritable to the positive state.

11. The electronic apparatus of claim 10 , wherein the at least one memory and the computer instructions are further configured, with the processor, to cause the electronic apparatus to:

cache the physical address and the logical address using a two-dimensional hash table.

12. The electronic apparatus of claim 11 , wherein the two-dimensional hash table includes:

a first dimensional hash table for mapping the physical address to the logical address and the data using the physical address as a key, and

a second dimensional hash table for mapping the logical address to the physical address by using the logical address as a key.

13. The electronic apparatus of claim 10 , wherein:

the logical address corresponds to one physical address or is prevented from corresponding to any physical addresses; and

the physical address corresponds to at least one of a plurality of logical addresses or is prevented from corresponding to any logical addresses.

14. The electronic apparatus of claim 10 , wherein the at least one memory and the computer instructions are further configured, with the processor, to cause the electronic apparatus to:

if the physical address corresponds to the logical address only, set the indicator to the positive state; and

if the physical address corresponds to a plurality of logical addresses, or it is undetermined whether the physical address corresponds to the logical address only, set the indicator to the negative state.

15. The electronic apparatus of claim 10 , wherein the at least one memory and the computer instructions are further configured, with the processor, to cause the electronic apparatus to:

in response to performing at least one of a snapshot operation and a deduplication operation on the data in the storage device, set the indicator to the negative state.

16. The electronic apparatus of claim 10 , wherein the at least one memory and the computer instructions are further configured, with the processor, to cause the electronic apparatus to:

in response to a request for a read operation on the data, determine whether the data is cached in the cache;

in response to determining that the data is absent from the cache,

duplicate the data from the storage device into the cache; and

set the indicator to the negative state.

17. A computer program product being tangibly stored on a non-volatile non-transitory computer-readable storage medium and including machine-executable instructions, the machine-executable instructions, when executed, causing a machine to perform a step of:

caching data from a persistent storage device into a cache;

caching a physical address and a logical address of the data in the persistent storage device into the cache;

caching an indicator into the cache;

setting the indicator to a positive state or a negative state to indicate whether the data is directly rewritable in the cache; and

in response to receiving an access request for the data, accessing the data cached in the cache using at least one of the physical address and the logical address, wherein accessing the data cached in the cache comprises:

in response to the access request being a rewrite request, determining whether the indicator is in the positive state or in the negative state;

in response to determining that the indicator is in the positive state, directly performing a rewrite operation on the data in the cache; and

in response to determining that the indicator is in the negative state,

caching data for rewriting in a further position in the cache, and

setting an indicator indicating whether the data for rewriting is directly rewritable to the positive state.

18. The computer program product of claim 17 , wherein caching the physical address and the logical address into the cache comprises:

caching the physical address and the logical address using a two-dimensional hash table.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (046366/0014) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060450/0306 →
RELEASE OF SECURITY INTEREST AT REEL 046286 FRAME 0653 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058298/0093 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 046286/0653 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 046366/0014 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2018
From: CUI, WEI; WANG, DENNY DENGYU; GAO, JIAN; ZHANG, LESTER; GONG, CHEN
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 045608/0001 →