Computing apparatus, node device, and server

1. A computing apparatus, comprising:

an internal interface circuit configured to couple to an internal apparatus using a first communication protocol, the first communication protocol comprising a communication protocol used by a system bus, and the internal apparatus comprising an apparatus sharing a resource with the computing apparatus using the system bus;

an external interface circuit configured to couple to an external apparatus using a second communication protocol, the second communication protocol comprising a network communication protocol; and

a cache coherence engine circuit separately coupled to the internal interface circuit and each general computing core circuit in at least one general computing core circuit and configured to selectively work in at least a first mode or a second mode, when the cache coherence engine circuit is set to be working in the first mode, the cache coherence engine circuit being further coupled to a protocol conversion circuit and the external interface circuit in sequence and configured to implement cache coherence among the internal apparatus, the external apparatus, and the computing apparatus, and the protocol conversion circuit being configured to perform protocol conversion between a protocol used by the cache coherence engine circuit and the second communication protocol, and when the cache coherence engine circuit is set to be working in the second mode, the cache coherence engine circuit being directly coupled to the external interface circuit and further configured to implement cache coherence between the computing apparatus and the internal apparatus.

2. The computing apparatus of claim 1 , wherein when the cache coherence engine circuit works in the second mode, the at least one general computing core circuit is configured to:

implement a computing function together with the internal apparatus; or

perform communication control between the internal apparatus and the external apparatus.

3. The computing apparatus of claim 2 , further comprising a communication acceleration circuit and a peripheral control circuit, and when the cache coherence engine circuit works in the second mode, the communication acceleration circuit is separately coupled to the peripheral control circuit and the external interface circuit, and the peripheral control circuit is coupled to the cache coherence engine circuit.

4. The computing apparatus of claim 3 , wherein the communication acceleration circuit is integrated into the external interface circuit.

5. The computing apparatus of claim 1 , wherein the protocol conversion circuit is integrated into the external interface circuit.

6. The computing apparatus of claim 1 , further comprising a system on chip or a processor.

7. A node device, comprising:

a processor; and

at least one first computing apparatus, and each first computing apparatus comprising:

an internal interface circuit configured to couple to the processor using a first communication protocol comprising a communication protocol used by a system bus, and the processor sharing a resource with the at least one first computing apparatus using the system bus;

an external interface circuit configured to couple to an external apparatus using a second communication protocol comprising a network communication protocol; and

a cache coherence engine circuit separately coupled to the internal interface circuit and each general computing core circuit in at least one general computing core circuit and configured to selectively work in at least a first mode or a second mode, when the cache coherence engine circuit is set to be working in the first mode, the cache coherence engine circuit being further coupled to a protocol conversion circuit and the external interface circuit in sequence and configured to implement cache coherence among the processor, the external apparatus, and the at least one first computing apparatus, and the protocol conversion circuit being configured to perform protocol conversion between a protocol used by the cache coherence engine circuit and the second communication protocol, and when the cache coherence engine circuit is set to be working in the second mode, the cache coherence engine circuit being directly coupled to the external interface circuit and further configured to implement cache coherence between the at least one first computing apparatus and the processor.

8. The node device according to claim 7 , wherein when the cache coherence engine circuit works in the second mode, the at least one general computing core circuit is configured to:

implement a computing function together with the processor; or

perform communication control between the processor and the external apparatus.

9. The node device of claim 8 , wherein the at least one first computing apparatus further comprises a communication acceleration circuit and a peripheral control circuit, when the cache coherence engine circuit works in the second mode, the communication acceleration circuit being separately coupled to the peripheral control circuit and the external interface circuit and the peripheral control circuit being coupled to the cache coherence engine circuit.

10. The node device of claim 9 , wherein the communication acceleration circuit is integrated into the external interface circuit.

11. The node device of claim 7 , wherein the protocol conversion circuit is integrated into the external interface circuit.

12. The node device of claim 7 , wherein the at least one first computing apparatus comprises a system on chip or another processor.

13. A server, comprising at least two node devices, and each node device comprising:

a processor; and

at least one first computing apparatus, and each first computing apparatus comprising:

an internal interface circuit configured to couple to the processor using a first communication protocol comprising a communication protocol used by a system bus, and the processor sharing a resource with the at least one first computing apparatus by using the system bus;

an external interface circuit configured to couple to an external apparatus using a second communication protocol comprising a network communication protocol; and

a cache coherence engine circuit separately coupled to the internal interface circuit and each general computing core circuit in at least one general computing core circuit and configured to selectively work in at least a first mode or a second mode, when the cache coherence engine circuit is set to be working in the first mode, the cache coherence engine circuit being further coupled to protocol conversion circuit and the external interface circuit in sequence and configured to implement cache coherence among the processor, the external apparatus, and the at least one first computing apparatus, and the protocol conversion circuit being configured to perform protocol conversion between a protocol used by the cache coherence engine circuit and the second communication protocol, when the cache coherence engine circuit is set to be working in the second mode, the cache coherence engine circuit being directly coupled to the external interface circuit and further configured to implement cache coherence between the at least one first computing apparatus and the processor, and an external interface circuit of at least one first computing apparatus of each node device being coupled to an external interface circuit of at least one first computing apparatus of another node device.

14. The server of claim 13 , further comprising a switch, and an external interface circuit of at least one first computing apparatus of at least one node device being coupled to an external interface circuit of at least one first computing apparatus of at least one another node device using the switch.

15. The server of claim 13 , wherein when the cache coherence engine circuit works in the second mode, the at least one general computing core circuit is configured to:

implement a computing function together with the processor; or

perform communication control between the processor and the external apparatus.

16. The server of claim 15 , wherein the at least one first computing apparatus further comprises a communication acceleration circuit and a peripheral control circuit, when the cache coherence engine circuit works in the second mode, the communication acceleration circuit being separately coupled to the peripheral control circuit and the external interface circuit, and the peripheral control circuit being coupled to the cache coherence engine circuit.

17. The server of claim 16 , wherein the communication acceleration circuit is integrated into the external interface circuit.

18. The server of claim 13 , wherein the protocol conversion circuit is integrated into the external interface circuit.

19. The server of claim 13 , wherein the at least one first computing apparatus further comprises a system on chip.

20. The server of claim 13 , wherein the at least one first computing apparatus further comprises another processor.