IP Library Granted Patent US 10,754,706
Granted Patent B1
US 10,754,706 · App. 15/954,032 · Granted Aug 25, 2020

Task scheduling for multiprocessor systems

Inventors: Jinghui Mo (Annandale, VA); Ananya Ojha (Dunn Loring, VA); Will Hurwood (Washington, DC); Huadong Xia (McLean, VA)
Assignee: MicroStrategy Incorporated
G06F9/5088G06F9/48G06F9/485G06F9/4843G06F9/4856G06F9/4881G06F9/4887G06F9/50G06F9/5005G06F9/5061G06F9/5083
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Quick Facts
Patent No.
US 10,754,706
App. No.
15/954,032
Granted
Aug 25, 2020
Kind
B1
Abstract

Methods, systems, and apparatus, including computer-readable storage devices, for task scheduling in a multiprocessor system. The processors of a multiprocessor system are partitioned into two groups, a first group of processors that preferentially execute new, short-running tasks and a second group of processors that preferentially execute suspended, long-running tasks. A scheduler of the multiprocessor system maintains queues of new and suspended tasks, suspends tasks, and assigns tasks to the processors according to their group preference. By designating different processors to preferentially execute new, short-running tasks or suspended, long-running tasks, the multiprocessor system may more efficiently manage workloads that contain a mixture of task types.

Claims (65)

1. A method comprising:

assigning, by a multiprocessor system, hardware processors of the multiprocessor system to form a first group of hardware processors and a second group of hardware processors;

assigning, by the multiprocessor system, the first group of hardware processors to give priority to tasks in a first task queue including tasks that have executed for less than a predetermined amount of time;

assigning, by the multiprocessor system, the second group of hardware processors to give priority to tasks in a second task queue including tasks that have executed for at least the predetermined amount of time;

determining that a particular task in the first task queue has executed for at least the predetermined amount of time; and

in response to determining that the particular task in the first task queue has executed for at least the predetermined amount of time:

suspending execution of the particular task by the hardware processors in the first group;

removing the particular task from the first task queue; and

adding the particular task to the second task queue for execution by the hardware processors in the second group.

2. The method of claim 1 , wherein assigning the hardware processors comprises assigning different amounts of processors to the first group and the second group.

3. The method of claim 2 , further comprising:

determining that the amounts of hardware processors in the first group and the second group should be changed; and

changing the assignments of hardware processors in the multiprocessor system among the first group and the second group to satisfy a predetermined relationship.

4. The method of claim 1 , wherein assigning the first group of hardware processors to give priority to tasks in the first task queue comprises assigning the hardware processors in the first group to execute tasks in the first task queue until no more tasks are available in the first task queue, then executing tasks in the second task queue; and

wherein assigning the second group of hardware processors to give priority to tasks in the second task queue comprises assigning the hardware processors in the second group to execute tasks in the second task queue until no more tasks are available in the second task queue, then executing tasks in the first task queue.

5. The method of claim 1 , further comprising prioritizing the tasks in the first task queue based on (i) an order of submission of jobs corresponding to the tasks, and (ii) relationships among the tasks.

6. The method of claim 1 , wherein the first task queue has multiple levels and tasks are prioritized according to the levels;

wherein the method comprises:

determining that execution of a first task in the first task queue generates a new second task, the first task being located in a first level of the multiple levels;

adding the second task to the first task queue in a second level of the multiple levels;

stopping execution of the first task and executing the second task using a hardware processor in the first group of hardware processors.

7. The method of claim 6 , wherein the method comprises:

updating the first task queue to indicate a relationship between the second task and the first task;

retaining working data of the first task on a processing stack accessible to the hardware processor executing the second task; and

after completing the second task, resuming execution of the first task.

8. The method of claim 1 , further comprising prioritizing the tasks in the second task queue based on an order in which tasks are added to the second task queue.

9. The method of claim 8 , wherein the tasks in the second task queue are further prioritized based on an identity, role, or credential of a user associated with a task in the second task queue.

10. The method of claim 1 , wherein the first task queue includes only tasks that have executed for less than the predetermined amount of time; and

wherein the second task queue includes only tasks that have executed for at least the predetermined amount of time.

11. The method of claim 1 , comprising operating a scheduler to (i) assign, based on the assignment of the assignment of the first group to give priority to tasks in the first task queue, tasks from the first task queue to be executed by hardware processors previously assigned to the first group and (ii) assign, based on the assignment of the second group to give priority to tasks in the second task queue, tasks from the first task queue to be executed by hardware processors previously assigned to the second group.

12. The method of claim 1 , wherein the assignment of the hardware processors to the first group and the second group is maintained over the course of execution of multiple tasks by the hardware processors.

13. The method of claim 1 , comprising using the assignment of the hardware processors to the first group and the second group to select a hardware processor to execute a task.

14. A system comprising:

multiple hardware processors of a multiprocessor system; and

one or more computer-readable media storing instructions that, when executed, cause the multiprocessor system to perform operations comprising:

assigning, by the multiprocessor system, hardware processors of the multiprocessor system to form a first group of hardware processors and a second group of hardware processors;

assigning, by the multiprocessor system, the first group of hardware processors to give priority to tasks in a first task queue including tasks that have executed for less than a predetermined amount of time;

assigning, by the multiprocessor system, the second group of hardware processors to give priority to tasks in a second task queue including tasks that have executed for at least the predetermined amount of time;

determining that a particular task in the first task queue has executed for at least the predetermined amount of time; and

in response to determining that the particular task in the first task queue has executed for at least the predetermined amount of time:

suspending execution of the particular task by the hardware processors in the first group;

removing the particular task from the first task queue; and

adding the particular task to the second task queue for execution by the hardware processors in the second group.

15. The system of claim 14 , wherein assigning the hardware processors comprises assigning different amounts of hardware processors to the first group and the second group.

16. The system of claim 14 , wherein assigning in the first group of hardware processors to give priority to tasks in the first task queue comprises assigning the hardware processors in the first group to execute tasks in the first task queue until no more tasks are available in the first task queue, then executing tasks in the second task queue; and

wherein assigning the second group of hardware processors to give priority to tasks in the second task queue comprises assigning the hardware processors in the second group to execute tasks in the second task queue until no more tasks are available in the second task queue, then executing tasks in the first task queue.

17. The system of claim 14 , wherein the first task queue has multiple levels and tasks are prioritized according to the levels;

wherein the operations comprise:

determining that execution of a first task in the first task queue generates a new second task, the first task being located in a first level of the multiple levels;

adding the second task to the first task queue in a second level of the multiple levels;

stopping execution of the first task and executing the second task using a hardware processor in the first group of hardware processors.

18. One or more non-transitory computer-readable media storing instructions that, when executed by one or more hardware processors of a multiprocessor system, cause the multiprocessor system to perform operations comprising:

assigning, by the multiprocessor system, hardware processors of the multiprocessor system to form a first group of hardware processors and a second group of hardware processors;

assigning, by the multiprocessor system, the first group of hardware processors to give priority to tasks in a first task queue including tasks that have executed for less than a predetermined amount of time;

assigning, by the multiprocessor system, the second group of hardware processors to give priority to tasks in a second task queue including tasks that have executed for at least the predetermined amount of time;

determining that a particular task in the first task queue has executed for at least the predetermined amount of time; and

in response to determining that the particular task in the first task queue has executed for at least the predetermined amount of time:

suspending execution of the particular task by the hardware processors in the first group;

removing the particular task from the first task queue; and

adding the particular task to the second task queue for execution by the hardware processors in the second group.

19. The one or more non-transitory computer-readable media of claim 18 , wherein the operations further comprise:

determining that the amounts of hardware processors in the first group and the second group should be changed; and

changing the assignments of hardware processors in the multiprocessor system among the first group and the second group to satisfy a predetermined relationship.

20. The one or more non-transitory computer-readable media of claim 18 , wherein assigning the first group of hardware processors to give priority to tasks in the first task queue comprises assigning the hardware processors in the first group to execute tasks in the first task queue until no more tasks are available in the first task queue, then executing tasks in the second task queue; and

wherein assigning the second group of hardware processors to give priority to tasks in the second task queue comprises assigning the hardware processors in the second group to execute tasks in the second task queue until no more tasks are available in the second task queue, then executing tasks in the first task queue.

Assignments (4)
CHANGE OF NAME Recorded Sep 19, 2025
From: MICROSTRATEGY INCORPORATED
To: STRATEGY INC
Reel/Frame 072910/0511 →
TERMINATION AND RELEASE OF PATENT SECURITY AGREEMENT AT REEL/FRAME: 056647/0687, REEL/FRAME: 057435/0023, REEL/FRAME: 059256/0247, REEL/FRAME: 062794/0255 AND REEL/FRAME: 066663/0713 Recorded Sep 26, 2024
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS SUCCESSOR IN INTEREST TO U.S. BANK NATIONAL ASSOCIATION, IN ITS CAPACITY AS COLLATERAL AGENT FOR THE SECURED PARTIES
To: MICROSTRATEGY INCORPORATED; MICROSTRATEGY SERVICES CORPORATION
Reel/Frame 069065/0539 →
SECURITY INTEREST Recorded Jun 22, 2021
From: MICROSTRATEGY INCORPORATED
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 056647/0687 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2018
From: MO, JINGHUI; OJHA, ANANYA; HURWOOD, WILL; XIA, HUADONG
To: MICROSTRATEGY INCORPORATED
Reel/Frame 046223/0371 →
Cited By (3)
US 12,246,733 US 12,254,351 US 12,572,440