Test apparatus and semiconductor chip

1. A test apparatus comprising:

a first path circuit coupled to a semiconductor chip through a first channel;

a second path circuit coupled to the semiconductor chip through a second channel; and

a tester coupled to the first channel and the second channel,

wherein the tester is configured to generate a turnaround delay detection value according to a read data which is output from the semiconductor chip in response to a read command, and generate delayed read data by delaying the read data according to a difference between an external turnaround delay value provided externally and the turnaround delay detection value.

2. The test apparatus of claim 1 , wherein the turnaround delay detection value corresponds to a time of from a timing when the tester outputs a write data and the read command to a timing when the read data is received to the tester.

3. The test apparatus of claim 1 , wherein the tester includes:

a delay circuit configured to generate a plurality of delay signals by delaying the read data;

a multiplexer configured to select one among the plurality of delay signals and output the selected delay signal as the delayed read data according to a control signal;

a period signal generator configured to generate a period signal according to a calibration enable signal, the write data, and the read data; and

a controller configured to generate the turnaround delay detection value according to the period signal and a clock signal and generate the control signal according to the external turnaround delay value and the turnaround delay detection value.

4. The test apparatus of claim 3 , wherein the delay circuit includes a plurality of flip flops configured to shift the read data or an output of a previous flip flop according to the clock signal.

5. The test apparatus of claim 3 , wherein the period signal generator includes:

a first logic gate configured to generate a first period signal according to the calibration enable signal and the write data; and

a second logic gate configured to generate a second period signal according to the calibration enable signal and the read data.

6. The test apparatus of claim 3 , wherein the controller includes:

a latch configured to generate a counting enable signal according to the period signal;

a counter configured to output a counting value of the clock signal as the turnaround delay detection value according to the counting enable signal; and

an operator configured to output an operation result value for a difference between the external turnaround delay value and the turnaround delay detection value as the control signal.

7. The test apparatus of claim 3 , wherein the tester further includes: a determination circuit configured to perform a test result determination operation by comparing the delayed read data with a reference data.

8. A test apparatus comprising:

a semiconductor chip coupled to a first channel and a second channel, and output a read data in response to a read command; and

a tester coupled to the semiconductor chip through the first channel and the second channel, configured to generate a turnaround delay detection value according to the read data and generate delayed read data by delaying the read data according to a difference between an external turnaround delay value provided externally from the test apparatus and the turnaround delay detection value,

wherein the turnaround delay detection value corresponds to a time of from a timing when the tester outputs a write data and the read command to a timing when the read data is received to the tester.

9. The test apparatus of claim 8 , wherein the tester includes:

a delay circuit configured to generate a plurality of delay signals by delaying the read data

a multiplexer configured to select one among the plurality of delay signals and output the selected delay signal as the delayed read data according to a control signal;

a period signal generator configured to generate a period signal according to a calibration enable signal, the write data, and the read data; and

a controller configured to generate the turnaround delay detection value according to the period signal and a clock signal and generate the control signal according to the external turnaround delay value and the turnaround delay detection value.

10. The test apparatus of claim 9 , wherein the delay circuit includes a plurality of flip flops configured to shift the read data or an output of a previous flip flop according to the clock signal.

11. The test apparatus of claim 9 , wherein the period signal generator includes:

a first logic gate configured to generate a first period signal according to the calibration enable signal and the write data; and

a second logic gate configured to generate a second period signal according to the calibration enable signal and the read data.

12. The test apparatus of claim 9 , wherein the controller includes:

a latch configured to generate a counting enable signal according to the period signal;

a counter configured to output a counting value of the clock signal as the turnaround delay detection value according to the counting enable signal; and

an operator configured to output an operation result value for a difference between the external turnaround delay value and the turnaround delay detection value as the control signal.

13. The test apparatus of claim 9 , wherein the tester further includes: a determination circuit configured to perform a test result determination operation by comparing the delayed read data with a reference data.