Multi-junction optoelectronic device with group IV semiconductor as a bottom junction
A multi-junction optoelectronic device and method of manufacture are disclosed. The method comprises providing a first p-n structure on a substrate, wherein the first p-n structure comprises a first base layer of a first semiconductor with a first bandgap such that a lattice constant of the first semiconductor matches a lattice constant of the substrate, and wherein the first semiconductor comprises a Group III-V semiconductor. The method includes providing a second p-n structure, wherein the second p-n structure comprises a second base layer of a second semiconductor with a second bandgap, wherein a lattice constant of the second semiconductor matches a lattice constant of the first semiconductor, and wherein the second semiconductor comprises a Group IV semiconductor. The method also includes lifting off the substrate the multi-junction optoelectronic device having the first p-n structure and the second p-n structure, wherein the multi-junction optoelectronic device is a flexible device.
1. A method for fabricating a multi junction optoelectronic device, the method comprising:
forming a multi junction structure on a substrate comprising:
providing a first p-n structure on the substrate using a first chemical vapor deposition process, wherein the first p-n structure comprises a first base layer of a first semiconductor with a first bandgap such that a lattice constant of the first semiconductor matches a lattice constant of the substrate, and wherein the first semiconductor comprises a Group III-V semiconductor;
providing a second p-n structure on the first p-n structure using a second chemical vapor deposition process, wherein the second p-n structure comprises a second base layer of a second semiconductor with a second bandgap, wherein a lattice constant of the second semiconductor matches the lattice constant of the first semiconductor, and wherein the second semiconductor comprises a Group IV semiconductor, wherein the second bandgap is less than the first bandgap;
depositing a support layer on the second p-n structure, the support layer comprising a back side window layer on the second p-n structure to form a textured surface, and a dielectric layer on the textured surface of the back side window layer, wherein the support layer is composed of one or more materials having a chemical resistance to acids; and
lifting the multi junction structure off the substrate, wherein the multi junction structure is configured such that the first p-n structure is closer than the second p-n structure to a side of the multi junction structure on which light is to be incident after the multi junction structure is lifted off the substrate.
2. The method of claim 1 , wherein the multi junction optoelectronic device is a flexible device.
3. The method of claim 1 , wherein the substrate comprises a GaAs wafer.
4. The method of claim 1 , wherein there is a first tunnel junction between the first p-n structure and the second p-n structure.
5. The method of claim 1 , wherein the first semiconductor comprises one or more of GaAs, AlGaAs, InGaP, InGaAs, AlInGaP, AlInGaAs, InGaAsP, AlInGaAsP, GaN, InGaN, AlGaN, AlInGaN, GaP, alloys thereof, or derivatives thereof.
6. The method of claim 1 , wherein the second semiconductor comprises one or more of Si, Ge, C, Sn, alloys thereof, or derivatives thereof.
7. The method of claim 1 , wherein the second semiconductor has a smaller energy gap than the first semiconductor.
8. The method of claim 1 , wherein one or both of the first p-n structure or the second p-n structure comprise a physically textured surface.
9. The method of claim 8 , wherein the physically textured surface is achieved by a lattice mismatch between at least two materials in the first p-n structure or the second p-n structure by using any of a Stranski-Krastanov process or a Volmer-Weber process.
10. The method of claim 1 , wherein the first p-n structure further comprises one or more p-n junctions.
11. The method of claim 1 , wherein the second p-n structure further comprises one or more p-n junctions.
12. The method of claim 1 , wherein the support layer further comprises one or more of a semiconductor contact layer, a passivation layer, a transparent conductive oxide layer, an anti-reflective coating, a metal coating, an adhesive layer, an epoxy layer, or a plastic coating.
13. The method of claim 1 , wherein at least one of the first p-n structure or the second p-n structure comprises a heterojunction.
14. The method of claim 1 further comprises providing a sacrificial layer on the substrate suitable for an epitaxial liftoff process.
15. The method of claim 14 , wherein the sacrificial layer comprises AIAs.
16. The method of claim 1 , further comprising applying an epitaxial lift off (ELO) process for lifting the multi junction structure off the substrate.
17. The method of claim 1 , wherein the first chemical vapor deposition process and the second chemical vapor deposition process are a same type of process.