DATA CENTER ENVIRONMENT WITH CUSTOMIZABLE SOFTWARE CACHING LEVELS
A method is described. The method includes configuring different software programs that are to execute on a computer with customized hardware caching service levels. The available set of hardware caching levels at least comprise L1, L2 and L3 caching levels and at least one of the following hardware caching levels is available for customized support of a software program L2, L3 and L4.
1 . An apparatus, comprising;
a processor comprising one or more cache circuits, at least one of the cache circuits comprising local cache resources and gateway logic circuitry, the gateway logic circuitry to:
a) determine which requests received by the cache circuit are to be directed to the local cache resources; and/or
b) determine which lower level cache resource that any of the following are to be directed to: i) a request that suffers a cache miss in the local cache resources; ii) a request received by the gateway logic circuitry that is not to receive service from the local cache resources; iii) an item that has been evicted from the local cache resources.
2 . The apparatus of claim 1 wherein the local cache resources comprise at least one of a level one (L1) cache, level two (L2) cache and a level three (L3) cache.
3 . The apparatus of claim 1 wherein the local cache resources comprise an L4 cache.
4 . The apparatus of claim 1 wherein the local cache resources comprise a memory side cache.
5 . The apparatus of claim 4 wherein the memory side cache comprises more than one memory side cache level.
6 . The apparatus of claim 4 wherein the memory side cache is implemented with a pluggable component.
7 . The apparatus of claim 6 wherein the memory side cache comprises at least one of:
a dynamic random access memory (DRAM) dual in-line memory module (DIMM);
DRAM disposed on a DIMM that also has non volatile memory.
8 . An apparatus, comprising:
a package comprising at least one processor semiconductor chip, one or more cache circuits residing within the package, at least one of the cache circuits comprising local cache resources and gateway logic circuitry, the gateway logic circuitry to:
a) determine which requests received by the cache circuit are to be directed to the local cache resources; and/or
b) determine which lower level cache resource that any of the following are to be directed to: i) a request that suffers a cache miss in the local cache resources; ii) a request received by the gateway logic circuitry that is not to receive service from the local cache resources; iii) an item that has been evicted from the local cache resources.
9 . The apparatus of claim 8 wherein the cache circuit is integrated within the processor semiconductor chip.
10 . The apparatus of claim 9 wherein the local cache resources correspond to any of an L1 cache, an L2 cache, an L3 cache, an L4 cache.
11 . The apparatus of claim 8 wherein the cache circuit is integrated in a substrate semiconductor die of a stacked memory chip structure, the stacked chip memory structure being the local cache resources.
12 . The apparatus of claim 8 wherein the apparatus of claim 8 is integrated into a computing system.
13 . The apparatus of claim 12 wherein the computing system is a server computer system.
14 . The apparatus of claim 13 wherein the computing system is coupled to a data center's edge cache.
15 . A machine readable storage medium containing program code that when processed by a computer system cause a method to be performed, the method comprising:
configuring different software programs that are to execute on a computer with customized hardware caching service levels, wherein, the available set of hardware caching levels at least comprise L1, L2 and L3 caching levels and at least one of the following hardware caching levels is available for customized support of a software program L2, L3 and L4.
16 . The machine readable storage medium of claim 15 wherein the configuring comprises programming gateway circuitry of a caching level that provides customized support of a software program.
17 . The machine readable storage medium of claim 15 wherein the configuring comprises configuring an artificial intelligence software program at least with lowest latency ones of the configurable caching levels.
18 . The machine readable storage medium of claim 15 wherein the configuring comprises configuring a software program that is indifferent to caching latency without caching support of at least the lowest latency ones of the configurable caching levels.
19 . The machine readable storage medium of claim 15 wherein the configuring comprises configuring a software program that tends not to utilize a data item after it has been evicted from a caching level without caching support from at least one level beneath the caching level.
20 . The machine readable storage medium of claim 15 wherein the hardware caching levels further comprise a memory side cache caching level.