Differential amplifier with extended bandwidth and THD reduction
View Patent ↗The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a differential amplifier in cascode configuration. An input transistor is coupled to an output transistor via a peaking inductor. The output transistor is also directly coupled to a degeneration resistor. There are other embodiments as well.
1. A system comprising:
an amplifier device comprising:
a first transistor comprising a first base terminal and a first collector terminal, the first base terminal being coupled to a first input;
a second transistor comprising a second base terminal and a second collector terminal, the second terminal base being coupled to a second input;
a first peaking inductor coupled to the first collector terminal;
a second peaking inductor coupled to the second collector terminal;
a third transistor comprising a third base terminal and a first emitter terminal, the first emitter terminal being coupled to the first peaking inductor;
a fourth transistor comprising a fourth base terminal and a second emitter terminal, the second emitter terminal being coupled to the second peaking inductor; and
a degeneration resistor coupled to the third base terminal and the fourth base terminal; and
a output proportional to an input, and the output coupled to the amplifier device.
2. The device of claim 1 wherein the first input and the second input comprise a pair of differential input signal.
3. The device of claim 1 wherein further comprising a voltage source coupled to the degeneration resistor.
4. The device of claim 1 wherein the first peaking inductor is associated with a bandwidth increase.
5. The device of claim 1 wherein the degeneration resistor is associated with a distortion reduction.
6. The device of claim 1 wherein the first transistor further comprises a third emitter terminal, the third emitter terminal being coupled to a degeneration resistor.
7. The device of claim 6 wherein the degeneration resistor is coupled to a bias current source.
8. The device of claim 1 wherein the third transistor further comprises a third collector terminal coupled to a load resistor.
9. The device of claim 8 wherein the third collector terminal is coupled to a first output.
10. The device of claim 9 wherein the fourth transistor further comprises a fourth collector terminal coupled to a second output.
11. The device of claim 10 wherein the first output and the second output comprise a differential output pair.
12. The device of claim 8 wherein the load resistor is coupled to a supply voltage.
13. A system comprising:
an amplifier device comprising:
a first transistor comprising a first gate terminal and a first drain terminal, the first gate terminal being coupled to a first input;
a second transistor comprising a second gate terminal and a second drain terminal, the second gate terminal being coupled to a second input;
a first peaking inductor coupled to the first drain terminal;
a second peaking inductor coupled to the second drain terminal;
a third transistor comprising a third gate terminal and a first source terminal, the first source terminal being coupled to the first peaking inductor;
a fourth transistor comprising a fourth gate terminal and a second source terminal, the second source terminal being coupled to the second peaking inductor; and
a resistive element coupled to the third gate terminal and the fourth gate terminal; and
an output coupled to an input, the output coupled to the amplifier device.
14. The device of claim 13 wherein the resistive element comprises a resistor divider.
15. The device of claim 13 wherein the first transistor comprises a NMOS transistor.
16. The device of claim 13 wherein the third gate terminal is directly coupled to the fourth gate terminal.
17. The device of claim 13 wherein the first transistor further comprises a third source terminal coupled to a degeneration resistor.
18. The device of claim 13 wherein the first peaking inductor and the second peaking inductor are matched.
19. A system comprising:
a differential cascode amplifier device comprising:
a first BJT transistor comprising a first base terminal and a first collector terminal and a first emitter terminal, the first base terminal being coupled to a first input;
a first degeneration resistor coupled to the first emitter terminal;
a second BJT transistor comprising a second base terminal and a second collector terminal and a second emitter terminal, the second terminal base being coupled to a second input;
a second degeneration resistor coupled to the second emitter terminal;
a first peaking inductor coupled to the first collector terminal;
a second peaking inductor coupled to the second collector terminal;
a third transistor comprising a third base terminal and a third emitter terminal, the third emitter terminal being coupled to the first peaking inductor;
a fourth transistor comprising a fourth base terminal and a fourth emitter terminal, the fourth emitter terminal being coupled to the second peaking inductor; and
a degeneration resistor coupled to the third base terminal and the fourth base terminal; and
an output coupled to an input, the output linearly proportional to the input, the input and the output coupled to the differential cascode amplifier device.
20. The device of claim 19 wherein the first degeneration resistor and the second degeneration resistor are matched.