IP Library Granted Patent US 10,453,540
Granted Patent B2
US 10,453,540 · App. 15/959,538 · Granted Oct 22, 2019

Method and apparatus to prioritize read response time in a power-limited storage device

Inventors: Xin Guo (San Jose, CA); Yu Du (Hangzhou, CN); Curtis Gittens (Vancouver, CA); David J. Pelster (Longmont, CO); Donia Sebastian (Fair Oaks, CA)
Assignee: Intel Corporation
G11C16/30G06F3/06G06F13/18G11C16/32G11C16/26
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Quick Facts
Patent No.
US 10,453,540
App. No.
15/959,538
Granted
Oct 22, 2019
Kind
B2
Abstract

A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.

Claims (46)

1. A solid-state drive comprising:

a non-volatile memory channel controller communicatively coupled to a non-volatile memory; and

a power management controller communicatively coupled to the non-volatile memory channel controller, the power management controller comprising:

logic to perform weighted round robin arbitration to prioritize a request from the non-volatile memory channel controller for a power credit for a host read command directed to the non-volatile memory to minimize the host read command latency in a power limited operation mode.

2. The solid-state drive of claim 1 , wherein the logic to perform weighted round robin arbitration to prevent starvation of another type of command directed to the non-volatile memory.

3. The solid-state drive of claim 1 , wherein, the non-volatile memory includes a plurality of non-volatile memory dies and the non-volatile memory channel controller includes a command queue per non-volatile memory die, the non-volatile memory channel controller to swap order and to adjust priority of the host read command in the command queue to prioritize the host read command.

4. The solid-state drive of claim 3 , wherein the non-volatile memory channel controller further comprises:

arbiter logic to perform weighted round robin arbitration to select the request to send to the power management controller for the power credit.

5. The solid-state drive of claim 4 , wherein the non-volatile memory channel controller to increase priority level of the request for the power credit while the request is pending.

6. The solid-state drive of claim 3 , wherein a priority level assigned to the host read command is higher than another priority level assigned to a host write command.

7. The solid-state drive of claim 1 , wherein the non-volatile memory is NAND Flash.

8. A method comprising:

issuing a request, by a non-volatile memory channel controller for a power credit for a host read command directed to a non-volatile memory; and

performing weighted round robin arbitration, by a power management controller to prioritize the request from the non-volatile memory channel controller for the power credit to minimize the host read command latency in a power limited operation mode of a solid-state drive.

9. The method of claim 8 , wherein performing weighed round robin arbitration to prevent starvation of another type of command directed to the non-volatile memory.

10. The method of claim 9 , further comprising:

swapping order of the host read command in a command queue per non-volatile memory die in the non-volatile memory; and

adjusting priority of the host read command in a command queue per non-volatile memory die in the non-volatile memory to prioritize the host read command.

11. The method of claim 10 , further comprising:

performing weighted round robin arbitration to select the request to send to the power management controller for the power credit.

12. The method of claim 11 , further comprising:

increasing, by the non-volatile memory channel controller, the priority of the request for the power credit while the request is pending.

13. The method of claim 9 , wherein a priority level assigned to the host read command is higher than another priority level assigned to a host write command.

14. The method of claim 9 , wherein the non-volatile memory is NAND Flash.

15. A system comprising:

a non-volatile memory channel controller communicatively coupled to a non-volatile memory;

a power management controller communicatively coupled to the non-volatile memory channel controller, the power management controller comprising:

logic to perform weighted round robin arbitration to prioritize a request from the non-volatile memory channel controller for a power credit for a host read command directed to the non-volatile memory to minimize the host read command latency in a power limited operation mode; and

a display communicatively coupled to a processor to display data stored in the non-volatile memory.

16. The system of claim 15 , wherein, the non-volatile memory includes a plurality of non-volatile memory dies and the non-volatile memory channel controller includes a command queue per non-volatile memory die, the non-volatile memory channel controller to swap order and to adjust priority of the host read command in the command queue to prioritize the host read command.

17. The system of claim 16 , wherein the non-volatile memory channel controller further comprises:

arbiter logic to perform weighted round robin arbitration to select the request to send to the power management controller for the power credit.

18. The system of claim 17 , wherein the non-volatile memory channel controller to increase priority level of the request for the power credit while the request is pending.

19. The system of claim 15 , wherein a priority level assigned to the host read command is higher than another priority level assigned to a host write command.

20. The system of claim 15 , wherein the non-volatile memory is NAND Flash.

21. At least one non-transitory computer-readable storage medium storing instructions that, when executed by a processor cause a system to:

issue a request, by a non-volatile memory channel controller for a power credit for a host read command directed to a non-volatile memory; and

perform weighted round robin arbitration, by a power management controller to prioritize the request from the non-volatile memory channel controller for the power credit for the host read command to minimize the host read command latency in a power limited operation mode of a solid-state drive and to prevent starvation of another type of command directed to the non-volatile memory.

22. The non-transitory computer-readable storage medium of claim 21 , further comprising:

swap order of the host read command in a command queue per non-volatile memory die in the non-volatile memory; and

adjust priority of the host read command in a command queue per non-volatile memory die in the non-volatile memory to prioritize the host read command.

23. The non-transitory computer-readable storage medium of claim 22 , further comprising:

perform weighted round robin arbitration, non-volatile memory channel controller, to select the request to send to the power management controller for the power credit.

24. The non-transitory computer-readable storage medium of claim 23 , further comprising:

increase a priority level of the request for the power credit while the request is pending.

25. The non-transitory computer-readable storage medium of claim 21 , wherein the non-volatile memory is NAND Flash.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 063815/0490 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2018
From: GUO, XIN; DU, YU; GITTENS, CURTIS; PELSTER, DAVID J.; SEBASTIAN, DONIA
To: INTEL CORPORATION
Reel/Frame 045867/0254 →
Continuity (1)
Related Publication 20190043593A1 · Feb 7, 2019