IP Library › Patent Application 15959548
Patent Application
App. No. 15/959,548

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

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Quick Facts
Patent No.
US None
App. No.
15/959,548
Abstract

A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

Claims (14)

1 . A semiconductor device comprising:

a first insulating layer;

a first oxide insulating layer over the first insulating layer;

an oxide semiconductor layer over the first oxide insulating layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

a second insulating layer over the first insulating layer, the source electrode layer, the drain electrode layer, and the oxide semiconductor layer;

a second oxide insulating layer over the oxide semiconductor layer;

a gate insulating layer over the second oxide insulating layer;

a gate electrode layer over the gate insulating layer; and

a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer,

wherein a side surface portion of the second insulating layer is in contact with the second oxide insulating layer,

wherein the gate electrode layer includes a first region and a second region that have different widths,

wherein the first region is located over the second region, and

wherein the first region has a width larger than that of the second region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2018
From: ASAMI, YOSHINOBU; OKAZAKI, YUTAKA; OKAMOTO, SATORU; SASAGAWA, SHINYA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 045629/0097 →