Radar transceiver with a switched local oscillator
Example radar apparatuses including a phase lock loop circuit used for processing both transmission signals and reflection signals are provided herein. An example apparatus includes a transmit signal generator electrically connected to an antenna and configured to generate a transmission signal at a transmit frequency, a receiver circuit electrically connected to the antenna and configured to receive a radar return signal and downconvert the radar return signal at a downconvert frequency for signal processing, and a phase lock loop circuit configured to be tuned to output both at the transmit frequency for transmission of the transmission signal by the antenna and the downconvert frequency for downconverting a frequency of the radar return signal for further signal processing. The transmit frequency is different from the downconvert frequency.
1. An apparatus comprising:
a transmit signal generator for a pulse compression radar, wherein the transmit signal generator is electrically connected to an antenna and configured to generate a transmission signal at a transmit frequency;
a receiver circuit electrically connected to the antenna and configured to receive a radar return signal and downconvert the radar return signal at a downconvert frequency for signal processing; and
a phase lock loop circuit configured to be tuned to output both at the transmit frequency for transmission of the transmission signal by the antenna and at the downconvert frequency for downconverting a frequency of the radar return signal for further signal processing, wherein the transmit frequency is different from the downconvert frequency, and wherein the output of the phase lock loop circuit repeatedly shifts between the transmit frequency and the downconvert frequency.
2. The apparatus of claim 1 , wherein the phase lock loop circuit has a loop bandwidth of at least 20 MHz.
3. The apparatus of claim 1 , wherein the phase lock loop circuit comprises an emitter-coupled logic (ECL) phase detector.
4. The apparatus of claim 3 , wherein the ECL phase detector has a phase detection frequency of at least 250 Mhz.
5. The apparatus of claim 1 further comprising:
a direct digital synthesizer (DDS) configured to supply a source frequency to the phase lock loop circuit.
6. The apparatus of claim 5 , wherein the DDS is configured to change the source frequency by generating a coherent sweep, and wherein the transmit frequency comprises a frequency sweep pulse based on the coherent sweep.
7. The apparatus of claim 6 , wherein the frequency sweep pulse comprises an up sweep or a down sweep.
8. A system comprising:
an antenna configured to transmit and receive radio frequency signals;
a radar transceiver circuit comprising:
a transmit signal generator electrically connected to the antenna and configured to generate a transmission signal at a transmit frequency;
a receiver circuit electrically connected to the antenna and configured to receive a radar return signal and downconvert the radar return signal at a downconvert frequency for signal processing; and
a phase lock loop circuit configured to be tuned to output both at the transmit frequency for transmission of the transmission signal by the antenna and at the downconvert frequency for downconverting a frequency of the radar return signal for further signal processing, wherein the transmit frequency is different from the downconvert frequency, and wherein the output of the phase lock loop circuit repeatedly shifts between the transmit frequency and the downconvert frequency.
9. The system of claim 8 , wherein the phase lock loop circuit has a loop bandwidth of at least 20 MHz.
10. The system of claim 8 , wherein the phase lock loop circuit comprises an emitter-coupled logic (ECL) phase detector.
11. The system of claim 10 , wherein the ECL phase detector has a phase detection frequency of at least 250 Mhz.
12. The system of claim 8 , wherein the radar transceiver circuit further comprises:
a direct digital synthesizer (DDS) configured to supply a source frequency to the PPL.
13. The system of claim 12 , wherein the DDS is configured to change the source frequency by generating a coherent sweep, and wherein the transmit frequency comprises a frequency sweep pulse based on the coherent sweep.
14. The system of claim 13 , wherein the frequency sweep pulse comprises an up sweep or a down sweep.
15. A method of operation for a radar transceiver circuit comprising:
generating a transmit frequency using a phase lock loop circuit;
generate a transmission signal by applying the transmit frequency to a source signal;
switching the phase lock loop circuit to a downconvert frequency; and
downconverting a radar return signal to an intermediate frequency by applying the downconvert frequency, wherein the transmit frequency is different from the downconvert frequency.
16. The method of claim 15 further comprising:
generating the source signal by a direct digital synthesizer (DDS);
transmitting the transmission signal from an antenna;
receiving the radar return signal at the antenna; and
processing the radar return signal at the intermediate frequency.
17. The method of claim 15 , wherein the phase lock loop circuit has a loop bandwidth of at least 20 MHz.
18. The method of claim 15 , wherein the phase lock loop circuit comprises an emitter-coupled logic (ECL) phase detector with a phase detection frequency of at least 250 Mhz.