Semiconductor structure and manufacturing method of the same
The present disclosure provides a semiconductor structure, including a logic region and a memory region. The memory region includes a first N th metal line of an N th metal layer, a magnetic tunneling junction (MTJ) over first N th metal line, a carbon-based layer between the first N th metal line and the MTJ, and a first (N+M) th metal via of an (N+M) th metal layer. A method of manufacturing the semiconductor structure is also disclosed.
1. A method for manufacturing a semiconductor structure, the method comprising:
forming a first N th metal line;
forming a carbon-based layer over the first N th metal line;
forming a planarization etch stop layer over the carbon-based layer;
forming a bottom electrode via in the carbon-based layer and the planarization etch stop layer;
forming a magnetic tunneling junction (MTJ) multilayer over the bottom electrode via;
patterning a MTJ cell by an ion beam etch, wherein a portion of the carbon-based layer is exposed from the planarization etch stop layer during the ion beam etch; and
forming a first (N+M) th metal layer over the MTJ cell,
wherein N is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.
2. The method of claim 1 , further comprising:
forming an inter layer dielectric over the first N th metal line prior to forming the carbon-based layer.
3. The method of claim 1 , wherein the patterning the MTJ cell comprises forming a hard mask pattern over the MTJ multilayer prior to the ion beam etch.
4. The method of claim 1 , wherein the ion beam etch stops at the carbon-based layer.
5. The method of claim 1 , wherein forming the carbon-based layer comprises depositing amorphous carbon, carbon, or diamond.
6. The method of claim 1 , further comprising forming a sidewall spacer covering the MTJ cell and contacting the carbon-based layer after patterning the MTJ cell.
7. A method for manufacturing a semiconductor structure, the method comprising:
forming a first N th metal line in a memory region and a second N th metal line in a logic region;
forming a carbon-based layer over the first N th metal line and the second N th metal line;
forming a planarization etch stop layer over the carbon-based layer;
forming a bottom electrode via in the carbon-based layer and the planarization etch stop layer;
forming a magnetic tunneling junction (MTJ) multilayer over the bottom electrode via;
patterning a MTJ cell by an ion beam etch, wherein the ion beam etch stops at the carbon-based layer in the logic region and the memory region, a portion of the carbon-based layer is exposed from the planarization etch stop layer; and
forming a first (N+M) th metal layer directly on the MTJ cell,
wherein N is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.
8. The method of claim 7 , further comprising:
removing the carbon-based layer in the logic region after patterning the MTJ cell.
9. The method of claim 7 , further comprising:
forming a sidewall spacer covering the MTJ cell subsequent to exposing the carbon-based layer from the planarization etch stop layer; and
removing the sidewall spacer in the logic region.
10. The method of claim 7 , wherein forming the carbon-based layer comprises depositing amorphous carbon, carbon, or diamond.
11. A method for manufacturing a semiconductor structure, the method comprising:
forming a carbon-based layer in a memory region and a logic region;
forming a planarization etch stop layer over the carbon-based layer;
forming a bottom electrode via in the carbon-based layer and the planarization etch stop layer;
forming a magnetic tunneling junction (MTJ) multilayer over the bottom electrode via; and
patterning a MTJ cell by an ion beam etch, wherein the planarization etch stop layer is at least partially removed and a portion of the carbon-based layer is exposed from the planarization etch stop layer during the ion beam etch, wherein the MTJ cell has a bottom width greater than a top width of the bottom electrode via.
12. The method of claim 11 , wherein a portion of the planarization etch stop layer remained subsequent to performing the ion beam etch, wherein the remained portion is in direct contact with a bottom surface of the MTJ cell.
13. The method of claim 12 , further comprising:
forming a sidewall spacer covering the MTJ cell and contacting the carbon-based layer in the memory region after patterning the MTJ cell; and
removing the sidewall spacer in the logic region.
14. The method of claim 13 , further comprising:
performing an ARC etch back operation to expose a top surface of the MTJ cell; and
removing the carbon-based layer in the logic region.
15. The method of claim 13 , wherein the remained portion of the planarization etch stop layer is laterally surrounded by the sidewall spacer.
16. The method of claim 13 , wherein the sidewall spacer is in direct contact with the carbon-based layer.
17. The method of claim 13 , wherein forming the sidewall spacer comprises:
forming a hard mask over the MTJ cell;
forming the sidewall spacer over a top surface of the hard mask; and
performing a planarization operation from above the MTJ cell, wherein the planarization operation stops at the hard mask.
18. The method of claim 12 , wherein a selectivity of the planarization etch stop layer to the carbon-based layer during the ion beam etch is greater than 3.
19. The method of claim 12 , wherein the planarization etch stop layer comprises silicon-rich oxide.
20. The method of claim 11 , further comprising:
conformably forming a dielectric layer over the memory region and the logic region; and
forming an anti-reflective coating (ARC) layer over the dielectric layer in the memory region and the logic region.