Semiconductor process modeling to enable skip via in place and route flow
A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.
1. A method for incorporating skip vias in a place and route flow of an integrated circuit design, the method comprising:
employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer; automatically adding the skip vias during the place and route flow; and
when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via in a newly generated physical layout.
2. The method of claim 1 , further comprising adding the skip vias in a layer-by-layer fashion.
3. The method of claim 1 , further comprising generating a list of failed skip vias.
4. The method of claim 1 , wherein the place and route tool is a program that automates back end of the line (BEOL) wiring.
5. The method of claim 1 , wherein the design rule includes width rules and minimum space rules.