Information handling system with priority based cache flushing of flash dual in-line memory module pool

1. An information handling system comprising:

a plurality of flash dual in-line memory modules including a first dual in-line memory module and a second dual in-line memory module;

a central processing unit to communicate with the flash dual in-line memory modules; and

a memory controller to communicate with the central processing unit and with the flash dual in-line memory modules, the memory controller to detect a flush command for a cache of the central processing unit, to detect that a value is written to a first flush hint register of a table, wherein the first flush hint register is associated with a first flash pool of the flash dual in-line memory modules, to detect that a value is written to a second flush hint register of the table, wherein the second flush hint register is associated with a second flash pool of the flash dual in-line memory modules, to determine whether the first flash pool is interleaved between more than one memory controller, to calculate relative flush hint addresses across the more than one memory controllers, and to flush first data for the first flash pool and second data for the second flash pool in the cache to flash dual in-line memory modules in order of priority based on a first priority of the first pool and a second priority of the second pool.

2. The information handling system of claim 1 , the memory controller further to map the first flush hint register to a first physical address within the flash dual in-line memory modules for the first flash pool.

3. The information handling system of claim 1 , wherein the first priority of the first flash pool is calculated based on a first number of input/output operations for the first flash pool and the second priority of the second flash pool is calculated based on a second number of input/output operations for the second flash pool.

4. The information handling system of claim 1 , the memory controller to issue a command to verify that all data in the cache has been stored in the flash dual in-line memory modules.

5. The information handling system of claim 1 , the memory controller further to parse a dual in-line memory module firmware interface table to extract the first and second flush hint registers, to associate the first flush hint register with attributes of the first flash pool, and to associate the second flush hint register with attributes of the second flash pool.

6. The information handling system of claim 5 , wherein the attributes for the first flash pool include the first flush priority, and hint register mapping.

7. A method comprising:

receiving, by a memory controller of an information handling system, a flush command for a cache of a central processing unit of the information handling system;

detecting, by the memory controller, that a value is written to a first flush hint register of a table within the central processing unit, wherein the first flush hint register is associated with a first flash pool of flash dual in-line memory modules of the information handling system;

detecting, by the memory controller, that a value is written to a second flush hint register of the table, wherein the second flush hint register is associated with a second flash pool of the flash dual in-line memory modules;

determining whether the first flash pool is interleaved between more than one memory controllers;

calculating relative flush hint addresses across the more than one memory controllers in response to the first flash pool being interleaved between more than one memory controllers; and

flushing, by the memory controller, first data for the first flash pool and second data for the second flash pool in the cache to flash dual in-line memory modules in order of priority based on a first priority of the first pool and a second priority of the second pool.

8. The method of claim 7 , further comprising:

mapping the first flush hint register to a first physical address within the flash dual in-line memory modules for the first flash pool.

9. The method of claim 7 , wherein the first priority of the first flash pool is calculated based on a first number of input/output operations for the first flash pool and the second priority of the second flash pool is calculated based on a second number of input/output operations for the second flash pool.

10. The method of claim 7 , further comprising:

issuing a command to verify that all data in the cache has been stored in the flash dual in-line memory modules.

11. The method of claim 7 , further comprising:

parsing a dual in-line memory module firmware interface table to extract the first and second flush hint registers;

associating the first flush hint register with attributes of the first flash pool; and

associating the second flush hint register with attributes of the second flash pool.

12. The method of claim 11 , wherein the attributes for the first flash pool include the first flush priority, and hint register mapping.

13. A method comprising:

parsing a dual in-line memory module firmware interface table to extract first and second flush hint registers;

associating the first flush hint register with first attributes of a first flash pool of a plurality of dual in-line memory modules of an information handling system;

associating the second flush hint register with second attributes of a second flash pool of the dual in-line memory modules;

mapping the first flush hint register to a first physical address within the flash dual in-line memory modules for the first flash pool;

mapping the second flush hint register to a second physical address within the flash dual in-line memory modules for the second flash pool;

writing a value to the first and second flush hint registers to indicate that data associated with the first and second flash pools are flushed to the flash dual in-line memory modules, wherein the data is in a cache of a central processing unit of the information handling system;

determining whether the first flash pool is interleaved between more than one memory controllers; and

calculating relative flush hint addresses across the more than one memory controllers in response to the first flash pool being interleaved between more than one memory controllers.

14. The method of claim 13 , further comprising:

storing a first priority value to the first flash pool; and

storing a second priority value to the second flash pool, wherein first data for the first flash pool and second data for the second flash pool in the cache to flash dual in-line memory modules in order of priority based on the first priority of the first pool and the second priority of the second pool.

15. The method of claim 13 , wherein the first priority of the first flash pool is calculated based on a first number of input/output operations for the first flash pool and the second priority of the second flash pool is calculated based on a second number of input/output operations for the second flash pool.

16. The method of claim 13 , wherein the first attributes for the first flash pool include the first flush priority, and hint register mapping for the first flash pool.

17. The method of claim 13 , wherein the second attributes for the second flash pool include the second flush priority, and hint register mapping for the second flash pool.