Apparatus and system for high speed keeper based switch driver
A keeper based switch driver can generate overlapping differential signals and increase a crossing point of the overlapping differential signals a first predetermined amount. Additionally, the keeper based switch driver can further increase the crossing point of the overlapping differential signals a second predetermined amount and limit signal swing to an absolute value of a drain-source voltage. A microprocessor can also be electrically connected to a DAC cell with keeper based switch driver through a performance detection circuit. The microprocessor can be configured to receive information from a performance detection circuit and control a current of a variable current source in a keeper bias circuit accordingly.
1. A keeper based switch driver, comprising:
circuitry configured to
generate overlapping differential signals,
increase a crossing point of the overlapping differential signals a first predetermined amount,
further increase the crossing point of the overlapping differential signals a second predetermined amount, and
limit signal swing to an absolute value of a drain source voltage.
2. The keeper based switch driver of claim 1 , wherein the crossing point of the overlapping differential signals is increased without introducing delay.
3. The keeper based switch driver of claim 1 , wherein the crossing point of the overlapping differential signals is increased by the first predetermined amount based on a skewed inverter pre-driver configuration.
4. The keeper based switch driver of claim 3 , wherein the skewed inverter pre-driver configuration includes a symmetrical pair of skewed inverter pre-drivers, a first skewed inverter pre-driver connected to a positive input terminal and a second skewed inverter pre-driver connected to a negative input terminal.
5. The keeper based switch driver of claim 4 , wherein each of the first skewed inverter pre-driver and the second skewed inverter pre-driver includes an n-channel metal-oxide-semiconductor (NMOS) device connected to a p-channel metal-oxide-semiconductor (PMOS) device that is larger than the NMOS device.
6. The keeper based switch driver of claim 1 , wherein the crossing point of the overlapping differential signals is further increased the second predetermined amount based on a keeper cell.
7. The keeper based switch driver of claim 6 , wherein the keeper cell is configured as a pull up device.
8. The keeper based switch driver of claim 6 , wherein the keeper cell is configured to have programmable current consumption.
9. The keeper based switch driver of claim 1 , wherein the limited signal swing corresponds to the drain-source voltage of the devices in the keeper cell.
10. The keeper based switch driver of claim 1 , wherein the circuitry is further configured to improve PAM-N eye quality, where N is an integer greater than one.
11. A system, comprising:
a keeper based switch driver including circuitry configured to
generate overlapping differential signals,
increase a crossing point of the overlapping differential signals a first predetermined amount,
further increase the crossing point of the overlapping differential signals a second predetermined amount, and
limit signal swing to an absolute value of a drain-source voltage; and
a microprocessor electrically connected to a performance detection circuit, the microprocessor including processing circuitry configured to
receive information from the performance detection circuit, and
control a current of a biasing circuit in the keeper based switch driver to control current consumption in at least part of the keeper based switch driver.
12. The system of claim 11 , wherein the received information includes a circuit condition of at least one component of the keeper based switch driver.
13. The system of claim 12 , wherein the circuit condition includes a temperature of at least one component of the keeper based switch driver.
14. The system of claim 11 , wherein the crossing point of the overlapping differential signals is increased without introducing delay.
15. The system of claim 11 , wherein the crossing point of the overlapping differential signals is increased the first predetermined amount based on a skewed inverter pre-driver configuration, the skewed inverter pre-driver configuration including a symmetrical pair of skewed inverter pre-drivers, a first skewed inverter pre-driver being connected to a positive input terminal and a second skewed inverter pre-driver being connected to a negative input terminal.
16. The system of claim 15 , wherein each of the first skewed inverter pre-driver and the second skewed inverter pre-driver includes an n-channel metal-oxide-semiconductor (NMOS) device connected to a p-channel metal-oxide-semiconductor (PMOS) device that is larger than the NMOS device.
17. The system of claim 11 , wherein the crossing point of the overlapping differential signals is further increased the second predetermined amount based on a keeper cell, the keeper cell being configured as a pull up device.
18. The system of claim 17 , wherein the keeper cell is configured to have programmable current consumption.
19. The system of claim 11 , wherein the limited signal swing corresponds to the drain-source voltage of the keeper cell.
20. The system of claim 11 , wherein the circuitry is further configured to improve PAM-N eye quality, where N is an integer greater than one.